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First circuit protects the IC against negative ( less than GND potential) spikes, second one protects both.Thank you for answer.
and I have another question.
I'm wondering what's the difference between with and without inverter.
Isn't the first circuit protects the IC against positive?When positive pulse ouccrs,MOS's gate becomes high and NMOS turns on.First circuit protects the IC against negative ( less than GND potential) spikes, second one protects both.
I guess VDD is the input.Hi,
I see VDD and VSS. But where is the input and the output?
What is the signal that should be protected aganst ESD?
Klaus