They are almost same..
First one uses the Capacitor between Bulk-Gate, second one uses an extra capacitor.
When ESD transient pulse appears, a current flows through the resistor and a voltage occurs between Gate-Source of NMOS transistors and this NMOS makes VDD-VSS short circuit in a temporary time slot.So protects the IC against ESD zapps.
They are almost same..
First one uses the Capacitor between Bulk-Gate, second one uses an extra capacitor.
When ESD transient pulse appears, a current flows through the resistor and a voltage occurs between Gate-Source of NMOS transistors and this NMOS makes VDD-VSS short circuit in a temporary time slot.So protects the IC against ESD zapps.
Makes sense.
And VDD is the signal that should be protected against ESD. Only power supply. No other signal is involved.
Although I think that supplies are not that problematic with ESD (external circuitry, big capacitors, fast capacitors, other load..) it surely is possible.
So it protects against overvoltage ... and reverse voltage.
Does anyone expect voltages higher than 10V (just as example) at VDD? with and wihtout protection..
I´m asking because ESD usually is in the range of kilovolts.