sharkies
Member level 5
Hi, I'm trying to figure out transistor area mismatch and Vt mismatch using cadence ADE.
I'm assuming that this is done in Monte Carlo...
It's my first time using this, any clearer directions?
How can I get those parameters to plotted?
Also, for a simple transistor, If I run mismatch instead of 'process &mismatch" , then my histogram shows that the simulation outputs(the transistor current) are all in a single bin. Do I have setup issues here?
I'm assuming that this is done in Monte Carlo...
It's my first time using this, any clearer directions?
How can I get those parameters to plotted?
Also, for a simple transistor, If I run mismatch instead of 'process &mismatch" , then my histogram shows that the simulation outputs(the transistor current) are all in a single bin. Do I have setup issues here?