how do I design a Configurable logic block of fpga in pspice

[rajrevanth61]

Hello Everyone,

I want to implement the basic operation such as AND, XOR or anything using the Configurable logic block of FPGA using pspice . How do I do this? Any kind of leads will be a great help to me.

Thanks

 

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A "CLB" in an FPGA is just a look up table i.e. an SRAM memory along with a register or two (e.g. old Xilinx 3000 series FPGAs had a 4-input lookup table and a register). The details of the implementation of said memory and the logic used to program the memory cells is proprietary to the FPGA vendor. I'm not aware of any open-source FPGA ASIC libraries, but I've never had a need to look for one.

Regards

 

[rajrevanth61]

Actually I need to implement any basic operation using this figure of clb.

 

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use a truth table to come up with the content of the SRAM for any given equation having up to 4 inputs.

 

[rajrevanth61]

Hello I am new to this using of clb, can you please explain me in more detail for the problem. Your answer will be really helpful for me.

Thanks

 

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AND gate

LUT_address = {A,B,C,D}
A & B = X
where C & D are don't care

A B C D | X
--------+---
0 0 x x | 0
0 1 x x | 0
1 0 x x | 0
1 1 x x | 1

So the Look Up Table (LUT) will have 0's everywhere except addresses where both A and B inputs are both 1.

 

[rajrevanth61]

is the above method possible using the pspice netlist?

 

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That I don't know, I'm assuming you can model an SRAM memory in pspice, but beyond that I'm not sure how you go about inputting signals to load the SRAM memory cells with the LUT values. I haven't used PSPICE/spice for almost 30 years.

 

[icoin13]

This is an open source FPGA architecture, I think this may help
https://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html