How do compilers interpret gates in a structural HDL adder?

[p11]

Suppose if i try to design a full adder using half adder .we will declare components for and gate , xor gates etc . My question is how the compiler will understand how to do the and operation , or operation . I mean if x,y are inputs to an and gate and y be its output then should we need to write y <= a and b; if yes , then how to write and where to write , plz upload a program as an example .

 

[ads-ee]

I'm sort of at a loss as to what your real question is. I'm not sure if you are confusing yourself with structural coding v.s. behavioral coding styles.

A synthesis tool uses a library of vendor primitives and maps the HDL to those primitives. If you specify an AND/OR/XOR etc gate in your HDL, then the synthesis tool looks for a gate that does that function in the vendor's primitive library.