How could I do ECO in fpga implementation!!!

[gauz]

I had a large design, and it's really time consuming to run the full flow through from synthesis to map to par, if I had run the flow for one time, and then I found some pads constraints need to be re-allocated, how could I got the new implement quickly, just as run ECO in asic design???
Must I rerun all the map, par again?
Thanks !

 

[echo47]

Sounds like you are talking about Xilinx ISE tools.
Try "incremental synthesis" and "resynthesize". See the XST User Guide.
Try "guide mode" during routing. See the Development System Reference Guide.

 

[gauz]

thank!
I use par.ncd file as the guide file and guide mode is set to leverage for both map and par, but it seems still timing consuming, no the feel of speed-up.

 

[karikalan_t79]

how xilinx fae result and xilinx webcase support,usually they support like this issuers