Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How Could I Design a Logic Circuit That Counts the Number of 1s in a PROM?

Status
Not open for further replies.

hpfake

Newbie
Joined
Oct 3, 2021
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
11
How Could I Design a Logic Circuit That Counts the Number of 1s in a PROM?
 
Last edited:

You want processor less design ?

Either way you need an address generator and then a decoder for each address
that indicates #1's at that address and take that result and add it to total.....

Program example -



Verilog example (hardware) -



You can use this to convert Verilog code back to schematic -



Regards, Dana.
 
Last edited:

Hi,

I guess this is a school project.
So what hardware do you have?
What programming language do you use?
What size and irganisation is the PROM?
What interface does it use?
Do you ave any timing requirements?

Klaus
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top