prakhars
Junior Member level 3
I have written a VHDL code, in which one of the input port is -
"Select64KB : STD_LOGIC_VECTOR(15 downto 0)"
now i want two component to be instantiated depending upon the condition whether select64KB(15) is '1' or '0';
i.e. <Component_1> is port mapped when Select64KB(15)='1';
and
<Component_2> is port mapped when select64KB(15)='0';
so how this can be achieved??????
"Select64KB : STD_LOGIC_VECTOR(15 downto 0)"
now i want two component to be instantiated depending upon the condition whether select64KB(15) is '1' or '0';
i.e. <Component_1> is port mapped when Select64KB(15)='1';
and
<Component_2> is port mapped when select64KB(15)='0';
so how this can be achieved??????