How Conditional Port Map in VHDL

[prakhars]

I have written a VHDL code, in which one of the input port is -

"Select64KB : STD_LOGIC_VECTOR(15 downto 0)"

now i want two component to be instantiated depending upon the condition whether select64KB(15) is '1' or '0';
i.e. <Component_1> is port mapped when Select64KB(15)='1';
and
<Component_2> is port mapped when select64KB(15)='0';

so how this can be achieved??????

 

[TrickyDicky]

you cant instantiate components dynamically like that. Imaging the VHDL is a circuit board, what youre asking is like trying to make a board where a chip gets phisically removed or added when a signal changes - that is impossible.

WHat you need to do in instantiate both, and then have some external control logic to send the signals to the correct component at the correct time (probably via a mux).

 

[prakhars]

Thank you very much TrickyDicky for your reply,... I need some more help from your side..

Actually there is only one component to be instantiated twice. I want them to work separately.
so can I use "Process" statement so that by using If-Else statement, I can assign same values to two different signals, then these signals can be used with two instantiations.

- - - Updated - - -

Thank you very much TrickyDicky for your reply,... I need some more help from your side..

Actually there is only one component to be instantiated twice. I want them to work separately.
so can I use "Process" statement so that by using If-Else statement, I can assign same values to two different signals, then these signals can be used with two instantiations.

 

[K-J]

Thank you very much TrickyDicky for your reply,... I need some more help from your side..

Actually there is only one component to be instantiated twice. I want them to work separately.
so can I use "Process" statement so that by using If-Else statement, I can assign same values to two different signals, then these signals can be used with two instantiations.

It doesn't matter if you want to instantiate two different components or two of the same component you can't do what you're describing as TrickyDicky said.

Some questions for you to ponder so that it will help people here to figure out a way to help you out further:
- Exactly why are you trying to instantiate two instance of the same component?
- What is the reason that a single instance of the same component can't be used?
- Assuming that you do need two instances, why do you think the port mapping needs to be changed dynamically?

In the end, it will likely be as was previously suggested that you must:
- Instantiate the two components
- Add a mux that selects the output from the appropriate component at run time

Kevin Jennings

 

[prakhars]

Actually I have designed a 1KB RAM on VHDL using a Hardware design approach..
My aim is to design 64KB RAM,. So what I thought is, first of all I will design 32KB RAM using 1KB RAM as a component with "Generate" command,..
Then will use this 32KB RAM as Component twice to have a complete 64 KB RAM.

Now for 64KB RAM, I have 65536 locations,. which needs 16 Address lines.
I will decode this 16 lines using a decoder and then will break 65536 lines into two parts ,.. one will contain first 32768 and second will contain remaining
32768 lines, as required by a 32KB RAM.

This 32 KB Rams will then further divide these 32768 lines into 32 Parts to be used by each 1KB Ram containing 1024 locations.

Now Problems arrives when my DECODER CODE FAILED TO GENERATE 65536 LINES OUT OF 16 ADDRESS LINES.
then I thought to check whether the MSB of the address is '1' or '0'. If it is '0' then use first 32KB Component, otherwise second 32KB Component.

I am not very much experienced with VHDL, so I am asking how this problem can be resolved.

Decoder code works fine upto 13x8192 decoding.

 

[std_match]

It is not completely clear what you want to do. If "select64KB" have a fixed value at compile time, you can have it as a generic instead of a port.
Then you can use it with "if xxx generate".

I hope you are doing this only to learn VHDL by simulation, and not for a real design. For a real FPGA design you should use the RAM-blocks generated by the FPGA vendor's tool, or follow their instructions about how to write generic VHDL code with an array so a RAM will be used. For an ASIC design you probably have to use the ASIC vendor's RAM generator.
With your approach the synthesis tool might not understand what you are trying to do, and that can lead to a waste of resources and a slow design.

Edit:
Ok, now I saw your other post about a decoder. I guess your are using it to build this RAM.
What you are trying to do doesn't make sense. You can do it as a simulated VHDL excercise, but you will not learn how to make a RAM that can be used in a real design.
Read the FPGA vendor's documentation about how to use the internal RAMs with VHDL.

 

[prakhars]

yes we are only intended to show a RAM Functionality, which can be verified by its Test-Bench. No particular device is to be used for physical Demonstration. Only want to show a RAM by its test Bench, that the Data can be stored at any location and can be read when we want.

Till Now we are done with 8KB RAM, and it is working absolutely fine.

SO if I use "SELECT64KB" as GENERIC instead a PORT, then will it help me setting Select64KB, according to me, at the time of Test Bench Generation.
Sometimes it also gives "Memory Conflict Error Message".

Also is there any software (Other than XILINX) related to VHDL, which can simply synthesize my VHDL code and give me appropriate Test Bench, without selecting a Device Particularly.

 

[std_match]

Also is there any software (Other than XILINX) related to VHDL, which can simply synthesize my VHDL code and give me appropriate Test Bench, without selecting a Device Particularly.

There is a free VHDL simulator, but I have not used it:

**broken link removed**