How choose wireload models for synthesis ?

[dr.farnsworth]

wire_load_table

Hi ,
How to decided which wire load model to choose for synthesis in design compiler ?

Thank you in advance

Regards
Dr.Farnsworth

 

[utmseng]

We depends on the gate count to choose the wire load model. As you know, the wire load model is a model which is based on the gate count sizes.

For a bigger size design, the wire_load_table will have bigger fanout length, vice versa.

For example,

wire_load_table("small_design") {
fanout_length( 1, 3);
fanout_length( 2, 11);
fanout_length( 3, 14);
fanout_length( 4, 17);

wire_load_table("big_design") {
fanout_length( 1, 100);
fanout_length( 2, 200);
fanout_length( 3, 280);
fanout_length( 4, 399);


You should be able to get the data from your foundary. They normally provide this data based on their previous design statistics.

You can set_wire_load_model and set_wire_load_mode in DC, and you can refer to the man page for more details.

Hope this helps!

 

[odeafeiner]

hi,

You'd better check the datasheet from your backend vendor(library supplier) for accurate wireload models settting. But people said there is no needed wireload models with advanced physical synthesis tools. no experience with this.

regards,

 

[utmseng]

Agreed.

Besides, from what I know, the latest version of DC do not need wireload model. We can directly read in the physical library into DC, and I suspect DC may do something similar to synopsys physical compiler's minimal physical compile.

 

[dr.farnsworth]

Thanks,

But do i need to specify wireload model in physical complier? i guess because the design compiler is not actual calculating but only estimating the wire delays from the technology library,we dont have to specify the wireload model ...correct me if iam wrong please..

 

[bronzefury]

If there are input or output pins on your chip, you might need to specify a wireload model so that the synthesis tool selects the correct buffer strength.

 

[mic_huhu]

If there are input or output pins on your chip, you might need to specify a wireload model so that the synthesis tool selects the correct buffer strength.

Yes.It is right

 

[utmseng]

Physical compiler does not need wire load model. It is able to use Steiner route to estimate the wire length since the tool should already have the placement information.

 

[jjww110]

wire load model is area-driven!!