How can we design a frequency doubler circuit?

[vlsi_freak]

Hello..

How can we design a frequency doubler circuit. (Other than using a PLL/DLL circuit)

Please share your thoughts and ideas.

Thanks

 

[vlsi_whiz]

Re: Frequency Doubler

To generate a freq doubler i think you need to generate outputs at both edges of the clock. Its like having one state machine give you o/p '1' at the rising edge and another at the falling edge. When both the state machine o/ps are combined, you get a clock/ signal which has double the freq of the input signal.

 

[ftfs2002]

Frequency Doubler

if you use the coding style ,the code you write can not be synthsis

 

[fpga_asic_designer]

Re: Frequency Doubler

Use PLL and DLL for a good clock doubler with best quality.

If you just want to build an easy doubler and don't care much about clitch... use xor gates.

delay1 DLYXL (.A(iclk), .Y(clk_d));
delay2 DLYXL (.A(clk_d), .Y(clk_1d));
delay3 DLYXL (.A(clk_1d), .Y(clk_2d));
delay4 DLYXL (.A(clk_2d), .Y(clk_3d));

assign clk_doubler = clk_3d ^ iclk;

as you can see, you can program the delay to adjust the duty cycle of the clock.

Regards