How can I synthesize my verilog program in Cadence?

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Cadence & Synopsys

Hi,

I'm a beginner in digital circuit design and have to design some digital circuits in Cadence to control my analog circuit. My question is, how can I synthesize my verilog program in Cadence, is CSI capable of synthesizing verilog codes? I found some tutorials about CSI (Cadence Synopsys Integration), I have the feeling that CSI can just do the opposite, that means, it can convert schematics into behaviorial models, or am I wrong? What about Verilog NC or XL? Can anyone recommend me a GOOD tutorial about synthesizing tools in Cadence and give me some advice about how to operate them?

thanks in advance
 

Cadence & Synopsys

try buildgate and pks . both are good tools from cadence for synthesis.
any my recommendation for synopsys Design complier for synthesis.
search good about PKS u will get more results
 

Cadence & Synopsys

I think synopsys' DC is the de-facto standard.
 

Re: Cadence & Synopsys

Synopsys's DC is most widely used Synthesis tool.
It is more powerfull than cadence's pks or buildgates
 

Re: Cadence & Synopsys

hi
you can refer this site.
hope this will help

**broken link removed**
 

Cadence & Synopsys

If the gate count < the 1million, the magam is the best tools,
If >1million , U may select the DCultra .
the Build gates of the cadence is the cheap tools than the Dc anf Magam.
 

Re: Cadence & Synopsys

hi, budy
pls try rtlcompiler from C@dence, and you'll get surprise.
less area/high speed/more capacitance.
as my opinion, better than dc-ultra/magma.
 

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