Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 always @(posedge clk,negedge reset) begin if(!reset) begin for(index=0;index<247;index=index+1) // for reading the elements in the row begin if (AddrA != 1110011110010000) //for cheking the end begin if(din[index] == 8'hFF // checking the element value if its '1' a[index]=a[index]+1; // array for voting and storing th position end end end AddrA=AddrA+247; end
No, the for loop doesn't work. You can only read one ram location per clock cycle.is this correct?
row_addr[7:0]
col_addr[7:0]
bram_addr[15:0] = {row_addr, coll_addr}
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