# How can i read the data from the BRAM (Coregen) , row major and know the position??

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#### gmk3

##### Newbie level 5
Hello every one..

I have stored a image in BRAM, i want to extract the position of all the values which has 'FF',
and store in a array at position it corresponds in the row.

1. how do i read the 1D array in row major and column major?
2. how do i know which position the value is 'FF' in the row?

Thank you so much in advance for the help.

##### Super Moderator
Staff member
assuming your BRAM data is packed without gaps between rows or columns.

BRAM address (linear) == (row * col) - 1

gives the relationship between any BRAM address (0-based) and a row/col (1-based). It doesn't mater whether it's organized row or column major. The difficulty here is if your minor direction is non-binary (with packed data) it becomes a true division problem as you have to perform a modulo operation to find the offset into the other direction. If you keep the minor direction binary then the upper bits are used as the major offset in the other direction.

e.g. in Row major order: 7 x 8 (row x col) row-1: uses BRAM 0-7 addresses, row-2: uses BRAM 8-15 addresses, etc. The bits that represent the BRAM address are [5:0]. The columns by [2:0] and the rows by [5:3].

If you don't have a binary minor modulo then you should use the next binary modulo above your minor to simplify the addressing. This only makes sense if you have the available RAM to spare as could end up being sparsely populated.

gmk3

### gmk3

Points: 2

#### gmk3

##### Newbie level 5

here is wat i have intrepreted:
is this correct?

Code Verilog - [expand]1
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always @(posedge clk,negedge reset)
begin
if(!reset)
begin
for(index=0;index<247;index=index+1)    // for reading the elements in the row
begin
if (AddrA != 1110011110010000)                     //for cheking the end
begin
if(din[index] == 8'hFF                   // checking the element value if its '1'
a[index]=a[index]+1;   // array for voting and storing th position
end
end
end
end

THankyou once again.

Last edited by a moderator:

#### FvM

##### Super Moderator
Staff member
is this correct?
No, the for loop doesn't work. You can only read one ram location per clock cycle.

gmk3

### gmk3

Points: 2

#### gmk3

##### Newbie level 5
Thankyou FvM..

BRAM depth is 59280 (240x247). That means i have to write it 247 times for row major and 240 times for column major..??!! please clarify!!

1. I have to check if value FF is present.
2. Then i have to calculate the mid point of the between the position of the value present and store it in a array to its corresponding location.

Please can you help me code this. I was trying to code the same i posted in previous message.

#### TrickyDicky

It means it will take 59280 clock cycles to read every value in the memory.

gmk3

### gmk3

Points: 2

#### vGoodtimes

There are certainly ways to boost write or read bandwidth. It just means more design time and complexity. What are your targets for the design?

#### gmk3

##### Newbie level 5
Thankyou vGoodtimes

My target is to detect a circular shape in a image.

#### TrickyDicky

do you have some matlab algorithm or C so you can compare any results you get from your verilog to your detection algorithm?
Is this image pre-processed/thresholded to separate background and target objects?

- - - Updated - - -

do you have some matlab algorithm or C so you can compare any results you get from your verilog to your detection algorithm?
Is this image pre-processed/thresholded to separate background and target objects?

gmk3

### gmk3

Points: 2

#### gmk3

##### Newbie level 5
Heya TrickyDicky

NO i am not comparing it with any algorithm of matlab or C.

I want to implement it on FPGA vertex 4.

yeah this is apre processed ( edge detected) image which is converted into .coe , loaded in BRAM.

#### TrickyDicky

Without a C or matlab version of the algorithm, how will you know if it's working?
I highly suggest you create a model, as this is quite a complex algorithm

gmk3

### gmk3

Points: 2

#### gmk3

##### Newbie level 5
Thankyou TrickyDicky

Yeah i have a embedded function written for the same.

#### TrickyDicky

What do you mean by "embedded function"?
You will need something to generate expected results when you test your FPGA code to ensure it is functionally correct BEFORE you put the code in the FPGA. ie. you will need a test bench for simulation

gmk3

### gmk3

Points: 2

#### gmk3

##### Newbie level 5
Thankyou TrickyDicky

yeah i understand what you are saying but thats too far for me rt now.. my question was how to write code for reading the elements in a row & column of BRAM and calculate the mid point between them.

Thank You again..

##### Super Moderator
Staff member
I already explained how the addressing has to work in post #2.

You need a clock and then generate addresses according to what I described as to how to use the bits in your BRAM address.

In your case you will want to use a 16-bit BRAM address, with 8-bits for row and 8-bits fro column. This means you never use the address values between 240-255 and 247-255, but doing otherwise (packing) will make the logic far to complex.

Just create address generator logic that has something like:
Code:
row_addr[7:0]
bram_addr[15:0] = {row_addr, coll_addr}
depending on which address you increment row_addr or col_addr, will access the data as either row or col major. Very simple.

You need to write some control logic (e.g. counters, FSM, etc) to iterate through all the memory locations. This can be done with a pair of row_addr/col_addr counters that rollover at 239 and 246, depending on row or col major you rollover one and increment the other. A row_col_major signal could be used to enable the correct rollover-increment relationship.

You don't seem to understand how to write a synchronous description of an address generator accessing a memory (based on the use of a for loop in a reset clause). I advise learning Verilog a bit better first. Learn how to properly code counters, multiplexers, etc from sites like https://asic-world.com/verilog/index.html. Avoid using for loops until you have a through grasp of how for loops are unrolled into parallel hardware (and not sequential hardware).

And please no PMs, I do not help people via PM. Use the forums instead.

Regards

gmk3

### gmk3

Points: 2

#### vGoodtimes

It sounds like the user is loading data from a coe file vs actual writes to the RAM (ROM?). In such a case, you should either fix the loaded data using a script, or implement some extra logic.

address translation is not that bad, simply: linearAddress = row*kNumColumns + col (or col*kNumRows + row depending on format). This is a small multiply+add, and may require 0-3 cycles to perform depending on clock rate. You should keep track of the x,y accesses to avoid a linear to row,col conversion later. That is a multiply+lookupTable (0-3 cycle operation), but now there is some actual design work involved. (div/mod by a constant can be implemented as multiplication by a fractional constant with a correction factor if needed) While I've implemented the multiply+LUT for other reasons, I can't think of an image processing case where you know the linear address and also DON'T know the x,y coordinate.

Or you should write a script to store your image as a 256x256 image and have the unused portions be non 0xFF values.

I'll assume that any performance level is ok and that 1 pixel/cycle is ok.

gmk3

### gmk3

Points: 2
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