Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How can I include a vhdl project which has a clock into Actel A3PE-EVAL_BRD1?

Status
Not open for further replies.

mobile-it

Advanced Member level 1
Joined
Apr 24, 2004
Messages
467
Helped
22
Reputation
44
Reaction score
8
Trophy points
1,298
Activity points
3,344
Anyone has some experience with this board?

I have difficulties with assigning pins to signals.

The clock is pin 26 or am I wrong?

When I download the stapl file from the examples into my fpga everything works fine, when I write my own vhdl file I can program my FPGA but it is not working.. I think this may be because of wrong clock assignment.. can anyone help me out?


thanks very much!
 

mobile-it

Advanced Member level 1
Joined
Apr 24, 2004
Messages
467
Helped
22
Reputation
44
Reaction score
8
Trophy points
1,298
Activity points
3,344
Re: Actel A3PE-EVAL_BRD1

Can someone please help me out?
 

mobile-it

Advanced Member level 1
Joined
Apr 24, 2004
Messages
467
Helped
22
Reputation
44
Reaction score
8
Trophy points
1,298
Activity points
3,344
Re: Actel A3PE-EVAL_BRD1

Nobody seems to have an answer to my question?

Can someone deliver me a step-by step manual how I can include a vhdl project wich has a clock into my actel fpga? especially the pin assignments... That will help me a lot. Does nobody work with Actel fpga's at this time???
 

zape

Full Member level 2
Joined
Jul 10, 2003
Messages
120
Helped
14
Reputation
28
Reaction score
5
Trophy points
1,298
Location
Spain
Activity points
1,043
Actel A3PE-EVAL_BRD1

First steps in your rationale should include the testing of the clock oscillator and if it goes to the right FPGA pin. It is an easy task!!, I have downloaded the schematics and you have a jumper (JP24) and the FPGA uses a flat pack package so you can test the FPGA clock pin.

First verify this and afterwards you may check your Actel design (sthg that should be trivial).
 

    mobile-it

    Points: 2
    Helpful Answer Positive Rating

mobile-it

Advanced Member level 1
Joined
Apr 24, 2004
Messages
467
Helped
22
Reputation
44
Reaction score
8
Trophy points
1,298
Activity points
3,344
Re: Actel A3PE-EVAL_BRD1

Thanks for your help... stupid I was not thinking about this myself...

I will check it soon.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top