hi
i want to write structural code for this serial multiplier and this D block is just defined as an delay element,how can i write synthesizable code for this element???
I assume you know how to wire VHDL code for an adder and multiplier. You also now know that a delay element is nothing but a flip-flop (Sarath666's reply above). So create a basic entity containing the adder, multiplier and the delay-element. Later instantiate this entity as many times as you want. Referring to your figure, you need to connect a delay-element between each instantiated basic entity so as to get your desired functionality.
in the way u said i should do this multiply in six clks but i want to write this code and put t in a code that execute in one clk/?
how would that possible?
i think its too messy
hi
i want to write structural code for this serial multiplier and this D block is just defined as an delay element,how can i write synthesizable code for this element??? View attachment 118535
in the way u said i should do this multiply in six clks but i want to write this code and put t in a code that execute in one clk/?
how would that possible?
i think its too messy
That highlighted red text should have told you that it wouldn't work in 1 clock cycle.
Have you studied digital design? You're issues seem to be more of a problem with that than with actually writing HDL (ignoring all the typos you post).
That highlighted red text should have told you that it wouldn't work in 1 clock cycle.
Have you studied digital design? You're issues seem to be more of a problem with that than with actually writing HDL (ignoring all the typos you post).
Oops I wasn't think of a serial multiplier in my previous response, so the loop is to accumulate and the other line is probably a carry to the next stage. Didn't the "thesis paper" have any explanation of the block diagram?
Oops I wasn't think of a serial multiplier in my previous response, so the loop is to accumulate and the other line is probably a carry to the next stage. Didn't the "thesis paper" have any explanation of the block diagram?
Based on the text the loop is feeding back the carry.
I don't do any serial multiplication in FPGAs as I normally use the DSP hard IP if I need to do any multiplication, so I'm not familiar with the details of serial multipliers.