moh_monem43
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How can I make simulation for inertial delay and transport delay?
I tried to execute these examples
Library ieee;
Use ieee.std_logic_1164.all;
Entity buf is
Port (a : in std_logic;
B : out std_logic);
End buf;
Architecture buf of buf is
Begin
b <= a after 20 ns;
end buf;
library ieee;
use ieee.std_logic_1164.all;
entity delay_line is
port (a : in std_logic;
b : out std_logic);
end delay_line;
architecture delay_line of delay_line is
begin
b <= transport a after 20 ns;
end delay line;
when simulated previous two examples, delay time didn’t appear on signals. Why??
I used MAX 7000S family
I tried to execute these examples
Library ieee;
Use ieee.std_logic_1164.all;
Entity buf is
Port (a : in std_logic;
B : out std_logic);
End buf;
Architecture buf of buf is
Begin
b <= a after 20 ns;
end buf;
library ieee;
use ieee.std_logic_1164.all;
entity delay_line is
port (a : in std_logic;
b : out std_logic);
end delay_line;
architecture delay_line of delay_line is
begin
b <= transport a after 20 ns;
end delay line;
when simulated previous two examples, delay time didn’t appear on signals. Why??
I used MAX 7000S family