Jun 3, 2005 #1 V vivek Member level 4 Joined May 19, 2005 Messages 69 Helped 10 Reputation 20 Reaction score 1 Trophy points 1,288 Activity points 2,040 hi how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit?
hi how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit?
Jun 3, 2005 #2 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 verilog tri0 Give here ur VHDL example for weak zero. I will write equivalent verilog for that!
Jun 4, 2005 #3 V vivek Member level 4 Joined May 19, 2005 Messages 69 Helped 10 Reputation 20 Reaction score 1 Trophy points 1,288 Activity points 2,040 verilog syntax weak hi in VHDL weak zero is one of the values which can be taken up by the std_logic data type. in verilog no such data type is there. then how can we model weak zero?
verilog syntax weak hi in VHDL weak zero is one of the values which can be taken up by the std_logic data type. in verilog no such data type is there. then how can we model weak zero?
Jun 6, 2005 #4 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 verilog weak 0 In VHDL for weak 0 we have 'H' whoes equivalent in Verilog is tri0
Jun 12, 2005 #5 P power-twq Full Member level 6 Joined Jun 10, 2005 Messages 373 Helped 8 Reputation 16 Reaction score 3 Trophy points 1,298 Activity points 4,550 weak 0 in verilog weak zero will be realized by weak driver, for example, in TSMC libs, X4 strongest driver, X1, X2, X3 moderate driver. XL weakest driver. vivek said: hi how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit? Click to expand...
weak 0 in verilog weak zero will be realized by weak driver, for example, in TSMC libs, X4 strongest driver, X1, X2, X3 moderate driver. XL weakest driver. vivek said: hi how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit? Click to expand...
Jun 12, 2005 #6 A AlexWan Full Member level 5 Joined Dec 26, 2003 Messages 304 Helped 8 Reputation 16 Reaction score 2 Trophy points 1,298 Activity points 2,692 weak pulldown in verilog Hi, power-twq I think that you maybe make a mistake. The lib of X1, X2, X3 ... are only for drive ability. In each process lib, there are some pad for weak output, such as pull-up pads and pull-down pads. You can request those datasheet from TSMC or SIMC etc. Good Luck
weak pulldown in verilog Hi, power-twq I think that you maybe make a mistake. The lib of X1, X2, X3 ... are only for drive ability. In each process lib, there are some pad for weak output, such as pull-up pads and pull-down pads. You can request those datasheet from TSMC or SIMC etc. Good Luck