library IEEE,<our_custom_lib>;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tri_st_buff_uart is
port (uart_rx : out std_logic;
rx_en : in std_logic;
uart_tx : in std_logic;
rx_tx : inout std_logic
);
end tri_st_buff_uart;
architecture tri_st_buff_uart_arc of tri_st_buff_uart is
begin
process (rx_en, rx_tx, uart_tx)
begin
if (rx_en = '1') then
uart_rx <= rx_tx;
rx_tx <= 'Z';
else
uart_rx <= '1';
rx_tx <= uart_tx;
end if;
end process;
end tri_st_buff_uart_arc;