How can I design a bi-directional port?

[u24c02]

Hi.

I want to know how can I design a bi-directional port?
As I know, in verilog, there are inout port.
But I'm not sure what can I just connect by wire?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
module test (value, var);
  inout value;
  output reg var;
 
  assign value = (condition) ? <some value / expression> : 'bz;
 
  always @(<event>)
  var = value;
 
endmodule

---

Is this synthesiable (design compiler ) code? If yes, then how to make port at physical design?

 

[artmalik]

Bi-directional ports are never part of "synthesizable" design. Actually you don't need them. Any digital design can be done with muxes to emulate a bidirectional system. The bi-directional ports are present in I/Os which are not synthesizable.
What is your design and what are you trying to do here?

 

[u24c02]

Thanks,
I willing to make I2c master and slave, I think they are used inout port.

 

[artmalik]

This will be custom design for I/Os. I have worked on this... it is simple I/Os for which you have to create a circuit design, write a functional model and generate a .lib through characterization tool. There is no "synthesis" way of doing this nor the tools will be supporting constructs like this.

 

[u24c02]

Thanks but I does not make sense , did you mean that the real physical I/O is made by mux? So don't think about port? If then, how we can make port real phsical port?

Actuall, in my experiance, in FPGA, I assined the pin also used bi-direction like above my example verilog code.

 

[artmalik]

ok ..you are trying to use an FPGA .... FPGA's have their own compilers and Verilog modeling constructs. The FPGA vendor will give you give you Verilog constructs which will be mapped to their FPGA circuit implementations. It differs from vendor to vendor, you will have to follow their guidelines as far as coding the module is concerned. They have special attributes in the compiler to handle these situations..... this is just mapping and no synthesis is done here.

 

[u24c02]

Got it.
But my question point is how can implement port using verilog at real physical IC.
Just using mux? What if just input port or out port?

 

[artmalik]

As I mentioned, the bi-directional Verilog model can implemented as in the Verilog construct modeling scheme in the FPGA compiler.one way is to code as
tran* ...modeling in Verilog.
tri_state ...modeling in Verilog.
But it has to map to compiler constructs for the FPGA compiler that you are using

 

[FvM]

I must confess that I don't get the point about "not synthesizable" bidirectional ports. Are you talking specifically about ASIC tools? I'm not aware of a programmable logic (CPLD, FPGA) compiler that won't be able to translate bidirectional port descriptions to reasonable hardware. The tools also model internal bidirectional nodes, but that's a different topic.

 

[u24c02]

Thanks FvM, but I don't meant about tool.
Basically we can make rtl top and the porrt is make by back end engineer.
so I don't know how it does make to real port.

 

[FvM]

I don't understand what your problem is. The code in post #1 is a valid bidirectional port description (one of many possible ways). What do you want to achieve beyond this example?

 

[dpaul]

I had implemented an in-out port using tri-state buffer in VHDL. It is pretty simple & straight fwd. I was also able to synth it as part of a larger design using Synopsys DC using the library our institute had. May be this can help you.

library IEEE,<our_custom_lib>;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
  
  entity tri_st_buff_uart is
      
      port (uart_rx : out std_logic;
            rx_en   : in std_logic; 
            uart_tx : in std_logic; 
            rx_tx   : inout std_logic
            );
      
  end tri_st_buff_uart;
  
  architecture tri_st_buff_uart_arc of tri_st_buff_uart is
      
      begin
          
          process (rx_en, rx_tx, uart_tx)
              
              begin
                  
                  if (rx_en = '1') then
                      uart_rx <= rx_tx;
                      rx_tx   <= 'Z';
                  else
                      uart_rx <= '1';
                      rx_tx   <= uart_tx;
                  end if;
                  
              end process;         
      
  end tri_st_buff_uart_arc;