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how can i access signals from differents entities within my code in VHDL?

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papetorh

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Hi thanks in advance for the help.

bit how can i access signals from differents entities within my code ? ( in VHDL)
 

TrickyDicky

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You have to pass them out of the entity in the port definition/port map. There is no other way.
 

papetorh

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Thank you so much for the quick answer. can you show me how can i do this with the port map command? Thanks again
 

TrickyDicky

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you need to add a port to your entity:

some_sig : out std_logic;

and then map it when you instantiate the component:

port map ( some_sig => some_other_sig);
 

std_match

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I don't recommend it, but I think the VHDL language allows you to do it with signals declared in a package.
I have not tested it, and I will not be surprised if some tools refuse to accept it, even if it is legal VHDL.

It should not be used in a design, but it could be a convenient way to temporarily route internal signals to pins for debugging/testing.
Using the "normal" way, it can be a lot of work to do it if the signals are several levels down.
 

BlackHelicopter

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Using the "normal" way, it can be a lot of work to do it if the signals are several levels down.

This is often cumbersome if port changes need to be made like you mentioned.. just curious does anyone know of an editor or IDE that auto-updates port maps and port declarations to make things easier?
 

aruipksni

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This is often cumbersome if port changes need to be made like you mentioned.. just curious does anyone know of an editor or IDE that auto-updates port maps and port declarations to make things easier?

1./ for simulation/verifications you can use signal spy in modelsim or questa see :
**broken link removed**

2./ you can try to use vhdl-2008 Hierarchical names feature. however you will probebly need latest tools if available to support this feature.
xilinx for example is not supporting vhdl-2008. they say the will support it in vivado 2014, but they are promissing to support it for years.

3./ you can of course use verilog which support this feature for years. also you can access vhdl signals/variables to verilog, something you can't do in vhdl-2008.
see example :
https://www.asic-world.com/verilog/syntax3.html
 

DFT_designer

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VHDL is a very rich description language, there are many methods to describe the same circuit.
Although your question is not clear, but I can give you 3 possible methods:
1) As said in the first answer by TrickyDicky: declare a principal entity in which you instantiate other entities. An input of the principal entity can be mapped to sub-entities using port map command.
2) As said in the fifth answer by std_match, package is also usable in this context.
3) Use a generic variable with an easy syntax:
entity AND
generic
(N : integer);
port
(A: in std_logic;
B: in std_logic;
S: out std_logic);
end AND;
After that do a generic map (similar to port map)

I would like also to comment this topic, VHDL is a description language and not a programming language: the concept of local and global variables used in computer science is not usable in VHDL.
Because it is a description of an electronic circuit and not just a code running in the simulator.

Regards
 

TrickyDicky

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I don't recommend it, but I think the VHDL language allows you to do it with signals declared in a package.
I have not tested it, and I will not be surprised if some tools refuse to accept it, even if it is legal VHDL.

It should not be used in a design, but it could be a convenient way to temporarily route internal signals to pins for debugging/testing.
Using the "normal" way, it can be a lot of work to do it if the signals are several levels down.

Signals in packages is perfectly legal VHDL. But, as you said, some tools will not compile them (Quartus for example, and altera have told me they will never support synthesis of these), but they are perfectly acceptable for simulation.
VHDL 2008 actually adds direct access to signals in any level of the hierchy via the << >> tags:

<< signal .tb.uut.o_n : std_logic >> -- hierarchical signal name
<< signal ^.^.a : std_logic >> -- signal a two levels above
<< variable @lib.pack.v : bit >> -- variable in a package pack

so you can do stuff like this:

alias buried_sig : std_logic is <<signal uut.some_signal_in_uut : std_logic>>;

But again, this is just a testbench thing, not a synthesisable one.
 

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