how assign statement can be implemented?

[yuenkit]

assign statement in always

I came across a statement saying why assignment statements should be avoided. One of the reason is

"Assign statements can be implemented in more than one way; less ambiguity is preferred"

the question is, how assign statement can be implemented? what are those "more than one way"?

 

[linuxluo]

synopsys remove_assigns

hi,
I think assign can be replaced by always block. so I dont understand what you mean. what book you check?

 

[deva_eda]

assign and always

Iam not sure if I cleary understood ur quey but

method 1 : for assign

assign anded_wire = a & b;

Method 2 : same assign using always is

always @ ( a or b)
anded_wire = a & b;

 

[yuenkit]

assign statements

the implementation here i guess is referring synthesis.
How synthesis tool implement different configuration for the assign statement

 

[jitendra]

Hi,
Synthesized netlist should not have assign statements.
Read article on synopsys solvnet for clarification and method to remove assign statement in netlist.
https://solvnet.synopsys.com/retrieve/003637.html

Let me know if you don't have solvnet account, I can download it and send it to you.

Regards,
Jitendra

 

[sree205]

I'm not sure that i understand completely.

assume you are writing a glue logic, in which one input port has to be connected to an output port.

according to the article, this is called a feedthrough. assume that this is necessary for the glue logic. how to implement this ? coz, assign or always statement, will both infer the feedthrough condition.anyway to get around this condition ?

 

[woodyplum]

in behav level, i don't think assign have any problem. the problem only occur when you implement in PR tools

 

[JesseKing]

in behav level, i don't think assign have any problem. the problem only occur when you implement in PR tools

I wanna know why problems will occur when PR?

Regards!

 

[archillios]

according to 'writing testbench' , assign is not as readable as always block, especially in complex combination logic block.

 

[omid219]

How can I avoid "assign" in cadence's synthesis tool?

Thanks

 

[kermit]

for RTL compiler:

in you srcipt;

include load_etc.tcl;## this script is from cadence Application Engineers, in /your_rc/etc/synth/ae_utils/load_etc.tcl
insert_io_buffers -remove_assigns