Spice is a modelling language and a simulator.
Spectre is a simulator from Cadence. Is spectre a language too? For example what is a spectre netlist?
Also, I am given to understand .scs files are spectre files.
Yet, how is it that I spectre is not compatible with a .scs model file?
I have a transistor model in a .scs file.
Yet when I try to run a analog simulation in .vams and include the model file as well, the parser throws an error saying the .scs file cannot be read.
If .scs is a spectre file, shouldn't the spectre simulator be able to read one of its own?
I can not understand what you want to mean at all.
Describe correctly using correct terminolgies.
"*.vams" is a Verilog-A(AMS) module.
Both Spectre Netlist and Verilog-AMS can be master netlist.
However it depends on what simulator you use.
What simulator do you use ?
If you use Cadence Spectre, master netlist has to be Spectre Netlist and Verilog-AMS is slave.
Some device models written by Cadence Spectre Syntax might call Verilog-A(AMS) modules in them.
If you use Cadence NCSim(so called AMSDesigner), Verilog-AMS can be master.
Anyway describe your situations correctly using correct terminolgies.