Please help me with the Cadence Schematic Errors

[nithinp]

I've been learning Cadence Virtuoso( I started learning Cadence today), and I've run into some frustrating errors while trying to create a simple CMOS inverter schematic. Despite carefully connecting the PMOS and NMOS transistors, ensuring no open nets, and placing the necessary pins (which is always a hassle), I keep encountering warnings about the VSS pin being in the global ground and annoying yellow blocks. Even after thorough checks for open nets, the errors persist, and it's seriously frustrating. After redesigning the circuit multiple times without understanding the underlying error, I eventually manage to resolve the issues, although without clear insight into the root cause. Although transient analysis plots successfully, I encounter errors during DC analysis, further complicating the troubleshooting process.

 

[Dominik Przyborowski]

Start with user guide. Virtuoso is delivered with high quality and comprehensive documentation. In case of issue, please show us your issue and what you want to achieve, too.

 

[dick_freebird]

gnd! should only be your primary top level ref ground,
never on-chip. Use vssd! for digital domain and vssa!
for on chip analog domain. vss! for top level vss pads /
bussing above those domains, connected to subsidiaries
by presistor, pinductor from layout measurements / extract.

Other bustedness wants some sort of exposition.

 

[nithinp]

I was able to avoid them. I just needed more practice