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How are Spice and Spectre different?

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amsdesign

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Correct me if I'm wrong.

Spice is a modelling language and a simulator.
Spectre is a simulator from Cadence. Is spectre a language too? For example what is a spectre netlist?
Also, I am given to understand .scs files are spectre files.
Yet, how is it that I spectre is not compatible with a .scs model file?
 

pancho_hideboo

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Spectre is a simulator from Cadence.
Is spectre a language too?
Yes.

Keysight ADSsim and GoldenGate simulator can read Cadence Spectre Netlist and HSPICE Netlits directly.

Cadence Spectre can read HSPICE Netlist directly.

Synopsys HSPICE can not read other language than HSPICE.

You can convert SPICE Netlist to Spectre Netlist by the following.
Code:
%spp -convert < spice_netlist.sp > spectre_netlits.scs

https://www.designers-guide.org/Forum/YaBB.pl?num=1284463608/3#3
This is Spectre Netlist.

https://www.designers-guide.org/Forum/YaBB.pl?num=1284463608/13#13
https://www.designers-guide.org/Forum/YaBB.pl?num=1284463608/19#19
This is HSPICE Netlist.

You can use HSPICE Netlist partially even in Spectre Netlist.

Also, I am given to understand .scs files are spectre files.
Yet, how is it that I spectre is not compatible with a .scs model file?
I can not understand what you want to mean at all.
Describe correctly.
 
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amsdesign

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I have a transistor model in a .scs file.
Yet when I try to run a analog simulation in .vams and include the model file as well, the parser throws an error saying the .scs file cannot be read.
If .scs is a spectre file, shouldn't the spectre simulator be able to read one of its own?
 

pancho_hideboo

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Yet when I try to run a analog simulation in .vams
I can not understand what you want to mean at all.
Describe correctly using correct terminolgies.

"*.vams" is a Verilog-A(AMS) module.

Both Spectre Netlist and Verilog-AMS can be master netlist.
However it depends on what simulator you use.

What simulator do you use ?

If you use Cadence Spectre, master netlist has to be Spectre Netlist and Verilog-AMS is slave.
Some device models written by Cadence Spectre Syntax might call Verilog-A(AMS) modules in them.

If you use Cadence NCSim(so called AMSDesigner), Verilog-AMS can be master.

Anyway describe your situations correctly using correct terminolgies.
 
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