16 bit signed adder
1.Use 2's complement all through the design,there is no need to convert to 1's complement.
2. If two data are both in [-1 1), and the number of bit is n, then use n+1 bit adder, there is no overflow. sum is in [-2 2),
3. n bit to n+1 bit cinversion: sign extended.
4. if you force sum into the region [-1,1), still use n+1 bit adder ,then find if MSB and the bit right to MSB(i.e. 2nd MSB) are the same(i.e. check sum[n+1] xor sum[n]) ,if same(logic result is 1'b0) ,no overflow,else if sum[n+1],sum[n] is 10, positive sum overflow occur, if sum[n+1],sum[n] is 01, negtive sum overflow(became positive).
Added after 12 minutes:
sorry, I make a mistake,
sum[n+1],sum[n] is 10 ,it meens the sum is negtive , but if you discard MSB, it becomes positive, overflow occur.
sum[n+1],sum[n] is 01 ,it meens the sum is positive, but if you discard MSB, it becomes positive, overflow occur.