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how about eco/spare cell?

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linuxluo

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spare cells rtl

Hi, all
Now I want to insert some spare cell in my desing, what's the flow?
and what tools can do it from syn@psys? or others?
Thanks.
 

philewar

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how to insert spare cells in rtl

linuxluo said:
Hi, all
Now I want to insert some spare cell in my desing, what's the flow?
and what tools can do it from syn@psys? or others?
Thanks.
Hi,

There's an article attacking this point in solvnet.
Just search.

Good luck.
 

kinysh

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Following is the article from solvenet.
but seems nothing valuable.

we add it by hand, connect every cells input to gnd or vcc.
ask layout to put all those net to the top metal.

any smart method?


*******************************************************
What is the flow for spreading spare gates evenly across a cell?


Question:

What is the flow for spreading spare gates evenly across a cell?

Answer:



1) Create a group of spare cells and mark as type spare.

In PlanetPL:

aprCmdCreateHierGroup
setFormField "Create Group" "Group Type" "Spare"
setFormField "Create Group" "Group Name" "group_name"
setFormField "Create Group" "Pattern" "select_pattern"
formOK "Create Group"

or in PlanetPL --> Groups --> Add to Group by Name

2) Place cells as normally done. (NTDL, TDL, SIP)

3) Spread spare cells among design

axgSpreadGroupCells or PostPlace --> Spread Group Cells


Former article name: 823
Version(s): 2000.2
 

ttspice

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1. We usually instantiate it by hand in the netlist.
2. Use a special name like SPARE_***
3. Tie all inputs to ground or power.
 

virtuosome

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we insert some spare cells by hand for change our netlist ,connect spare cells input to gnd or vcc,but we be ready to change one or two mask(top metal) to get our needed state.
 

philewar

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Sorry, I see the method regarding on spare cell in document from TSMC 0.25/0.18 refrence design flow.
 

joe2moon

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Which document ? Please ...

philewar said:
Sorry, I see the method regarding on spare cell in document from TSMC 0.25/0.18 refrence design flow.
May you tell more clearly ?

Which document do you mention about ?
(The file name of this document, for example)

Because I can not find that document .... :(

Thanks in advance !

ps: It's also good if you can PM me that document :eek:
 

linuxluo

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Hi,
Can you pm the the doc of TSMC design flow ?
It's very useful for me.
Thanks.
 

philewar

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The doc is "Spare Gate Handling Guide".

I'm sorry I DO not have the right to re-distribute this doc but I will spend some time on writing a brief introduction. Just waiting pls.

Thx.
 

sandusty

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1. write the spare module as mentioned above
2. call the spare module in RTL (with the spare percentage you have been assigned)
3. connect the clock input to the local clock, so the clock will be connected and balanced (if the block been gated, the spare will be gated too)
4. the rest are the same as posted above

you can add the spares after apr too
 

prisnow

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Usually there are two methods:
1.Add spare gates in RTL code by designer. It depends on the confidence of his design for a designer,such as addtional flops for improving FSM later.
You can define a common spare cell module,and instantiate in your design.

2. Add spare gates in netlist directly.

After all, the number of spare gates is about 1% of the total size.

It's my opinion. FYI
 

sandusty

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gerade:

If you are using DC, you need to put all spare in DONT_TOUCH

Backend tools toke care of the spares very efficient, but user might not get good control of the spares' location
 

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