hold time dbt - need explanation of a sentence

[dazzling_deepika]

hold time dbt

Can some body plz explain the following to me :

because the launch edge and the capture edge is the same edge, the hold timing check doesn't depend on the clock period.

how can launch edge and capture edge be the same for hold time?

 

[shelby]

hold time dbt

For a normal reg to reg path, the data is launched from the launch flop at a clock edge (call it x) and captured at the capture flop at the NEXT clock edge (x+1). If the clock delay to the capture flop is GREATER than the clock delay to launch flop + data delay then you will violate hold.

In other words, data launched at clock edge x must not be captured at capture flop by the same clock edge x, it should be captured by the next clock edge x+1.

This is why the launch edge and capture edge for hold checks are the same. Since the edges are the same, changing the frequency has no effect.

 

[dazzling_deepika]

Re: hold time dbt

hi,

I am sorry but I do not understand one thing:you are talking about edges x and x+1 .How can these be the same edges?

 

[heartfree]

hold time dbt

dazzling_deepika， in synchronous circuit, all flipflops are toggled by the same clock. at the same edge of clock, the neighbour flipflops latch their D input. if hold time is not meet, the updated data of previous flipflops will be latched by the next flipflops. that was not you want.

 

[sowmya005]

Re: hold time dbt

"data launched at clock edge x must not be captured at capture flop by the same clock edge x, it should be captured by the next clock edge x+1. " is what u said.
I hope it has to be
"data launched at clock edge x must be captured at capture flop by the same clock edge x, it should be not captured by the next clock edge x+1.

pl correct if i am wrong.
I hope its easy to put that
hold is the check to see that the present data is held for some min time so that the next data should not come fast and overwrites and the present data is lost.
Its more accurate to put that
the hold is checked just one clock cycle before setup is checked.