high voltage MOSFETS layouts and explanation

[ytliang]

high voltage MOSFETS

hello,

Could someone please give me some insights on high voltage mosfets layouts and why they are drawn that way?

Thanks

 

[mviswa]

Re: high voltage MOSFETS

Actually i dont know what is ment by HV mosfet ..

1. usually nowday day's all chips work at different voltages like core voltage & io voltage. usually io voltage voltages devices called TG devices , where tox more compare to core voltage transistors i.e. digital logic. TG MOSFETS will operate at more voltage than core Mosfets.

2. High voltage Mosfets also called DMOS/VDMOS transistrors. these transistor crosssection totally different from conventional mosfets to handle high voltage/high currents. In this transistors Drain extended under gate region more.

hello,

Could someone please give me some insights on high voltage mosfets layouts and why they are drawn that way?

Thanks

 

[sat]

high voltage MOSFETS

You mean Power-Semi.
Ask "International Rectifier" guys...

 

[ytliang]

Re: high voltage MOSFETS

Actually i dont know what is ment by HV mosfet ..

1. usually nowday day's all chips work at different voltages like core voltage & io voltage. usually io voltage voltages devices called TG devices , where tox more compare to core voltage transistors i.e. digital logic. TG MOSFETS will operate at more voltage than core Mosfets.

2. High voltage Mosfets also called DMOS/VDMOS transistrors. these transistor crosssection totally different from conventional mosfets to handle high voltage/high currents. In this transistors Drain extended under gate region more.

Could you please tell me why the drain extention under gate makes this a high voltage device?
Also, I also noticed some devices used wells instead of LDD for the drain extention. Is there any advantage/disadvantage for this?

thanks

 

[Colbhaidh]

Re: high voltage MOSFETS



The drain extension under the gate forms a lighlt doped region between drain and channel that the high voltage can be dropped across such that there is no punchthrough or breakdown between drain and source. These kinds of transistors are good for 40V and below. For higher voltages drift regions are required.

For very high voltage MOSFETs, a thick N- epi layer is used as a drift region to drop the high voltages. Filed rings are also used to shape the depletion to keep the high field edges of the depletion zone away from critical areas. Thus, the layout of very high voltage transistors is very different from conventional CMOS.[/img]

 

[curioush]

Re: high voltage MOSFETS

Hi Colbhaidh,

Is there any book or any resource that talks about high voltage MOSFETS layout techniques. I am a newbie to this area, I would like to understand in detail why they have been laid out in a particular way and what all precautions should be taken.

Thank you,
curioush

The drain extension under the gate forms a lighlt doped region between drain and channel that the high voltage can be dropped across such that there is no punchthrough or breakdown between drain and source. These kinds of transistors are good for 40V and below. For higher voltages drift regions are required.

For very high voltage MOSFETs, a thick N- epi layer is used as a drift region to drop the high voltages. Filed rings are also used to shape the depletion to keep the high field edges of the depletion zone away from critical areas. Thus, the layout of very high voltage transistors is very different from conventional CMOS.[/img]

 

[leo_o2]

I suggest reading design rule of HV MOS from foundry. Usually foundry will provide detailed guidelines.

 

[curioush]

Thanks Leo but the foundry rules does not explain why we do the poly field plating or any such techniques. If you any other source let me know

 

[leo_o2]

Poly field plating is used to increase Vgd breakdown voltage. It generates a thick oxide at the drain side.

 

[erikl]

If you any other source let me know

Find here a paper about HV MOS structures.

@Leo: I think poly field plate doesn't generate the TOX, but is placed over it.

 

[timof]

Re: high voltage MOSFETS

hello,

Could someone please give me some insights on high voltage mosfets layouts and why they are drawn that way?

Thanks

Are you asking about layout of one cell layout (determining such things as gate length, drift region length, etc.), or large-scale (mm) layout of metallization used to create a large-area device out of elementary cells?

The former is defined by the physical structure of the device required to achieve (along with non-layout parameters - implant doses, energies, etc.) certain device characteristics (breakdown voltage, specific Rdson value, etc.), and is fixed from the viewpoint of layout engineer or circuit designer.

The latter is usually of no interest to device engineers - but of great interest for layout engineers and designers. Large-area layouts allows to achieve a small Rdson value of the device by making its area large. But one should be very careful to make sure that the overall design is balanced, there are no current crowding areas (hot spots), the current through each wirebond (or bump/pillar) is the same, etc.

 

[leo_o2]

Yes， erikl. Your description is more accurate.
It is field oxide.

Find here a paper about HV MOS structures.

@Leo: I think poly field plate doesn't generate the TOX, but is placed over it.