High speed signals through long routing.

[kenambo]

Hi all

I need to pass high speed clock through long layout routing and i want my dutycycle to be in minimum variation.

I am using buffers for this. But across the corners duty cycle varies heavily.

Is ther any special care to be taken care in the layout..

thanks

 

[erikl]

... I am using buffers for this. But across the corners duty cycle varies heavily.

Is ther any special care to be taken care in the layout..

You can't avoid the gate delay variation from distributed buffers. But if you can use a local buffer chain with only one single output driving the total clock routing net, you'd just get RC delays, which vary less across the corners.

 

[kenambo]

yeah of course one get RC delays.. But the duty cycle variation is much after layout extraction.

And expected cap value from the layout is in range...

still i am not getting the results after extraction which i have got in schematics.

the distance between the buffers is 100um .

Any Advice?

 

[erikl]

still i am not getting the results after extraction which i have got in schematics.
...
Any Advice?

You'll never get the same post-layout results as the pre-layout results.

Use a buffer chain with a stronger buffer at the end.

 

[kenambo]

Hi thanks for your comment..

Actually the reason for dutycycle variation is, the coupling of another high speed signal which passes nearby.

and i have a shielding between these two signals.. still i am getting fluctuations because of that signal.

So how to avoid the coupling effect completely or minimum coupling..?

thanks

 

[erikl]

... coupling of another high speed signal which passes nearby.

and i have a shielding between these two signals.. still i am getting fluctuations because of that signal.

So how to avoid the coupling effect completely or minimum coupling..?

As always: still better shielding (not only sidewards, but additionally on top and bottom, if possible) and/or more spacing to the coupling signal.

Another method is using anti-phase signals - either for the coupling or the coupled signal.

 

[haykding]

can you explain how the other high speed signal causes duty cycle variation ? can you show some waveforms ?

 

[erikl]

can you explain how the other high speed signal causes duty cycle variation ?

As kenambo suspected above: the coupling from another signal might add, and so prolong or shorten the active phase.

can you show some waveforms ?

No, you'd better ask kenambo.

 

[kenambo]

can you explain how the other high speed signal causes duty cycle variation ?

Yeah as erikl explained above... it increases the dutycycle of the high speed clock to go to 60% when the coupling signal transitions from either 0 to 1 or 1 to 0. And the clock remains 55% when the other signal is zero that is i pass zero through the other path.

Hope you understand the scenario.

can you show some waveforms ?

My waveforms not uploading properly.

thanks