Sep 10, 2012 #1 G girih192002 Full Member level 2 Joined Aug 4, 2007 Messages 130 Helped 19 Reputation 38 Reaction score 11 Trophy points 1,298 Location India Activity points 2,115 Hi, I am just confusing with below attached picture. I have some doubt. This is SerDes architecture. 1. Here How 8b/10b and 16b/20b encoded signal is converted into 8:2 multiplexer ? actually ODD parallel inputs to EVEN parallel outputs 2. Why do we need to generated always ODD and EVEN signal at output of Serializer ? If you have any architecture for 8b/10b encoding then, please, suggest me those pipelin topoloy papers. thank you Attachments SerDes.png 119.4 KB · Views: 75
Hi, I am just confusing with below attached picture. I have some doubt. This is SerDes architecture. 1. Here How 8b/10b and 16b/20b encoded signal is converted into 8:2 multiplexer ? actually ODD parallel inputs to EVEN parallel outputs 2. Why do we need to generated always ODD and EVEN signal at output of Serializer ? If you have any architecture for 8b/10b encoding then, please, suggest me those pipelin topoloy papers. thank you
Sep 10, 2012 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,487 Helped 14,756 Reputation 29,794 Reaction score 14,121 Trophy points 1,393 Location Bochum, Germany Activity points 298,375 Even and odd is simply related to a double data rate topology that is outputting data at double the C2 clock rate.
Even and odd is simply related to a double data rate topology that is outputting data at double the C2 clock rate.