Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

High speed OP-amp PCB layout constraint

Status
Not open for further replies.

arunmaran10

Junior Member level 2
Joined
Jan 2, 2014
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,435
Hi all,
I am using High speed op-amp for DAC board, is there any routing contraint(Say cutout ground plane beneath IC Input Pin). please suggest some some layout constraint for this.



Regards,
Arunmaran
 

Some high impedance inputs can be affected by the capacitance between the Pad and the ground plane (couples HF noise), but it is the minority, I second the recommendation to read the data sheets.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top