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high speed comparator design problem.

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kkkhunter

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3V-0.6um cmos process, less than 20uA quiescent current and switch-c comparator cannot be used. SO which comparator circuit should be better? An OP without compensation is just OK? And under the restriction above, how about the limit of the comparator performance?

And how to measure the comparator speed? I knew that AV(0)*3dB-bandwidth can describe the small signal speed. Is that all?

Added after 36 minutes:

By the way, the comparator is expected to have response with less than 3mV input variation in about 50ns at least. And faster is better.
 

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