High speed clock divider

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Ayyanar M

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Hi,

I am designing the PLL for 5GHz-6GHz applications and the reference frequency as 20MHz. So i need the divider for the range from 250-300. Is it possible to design in digital? If yes, anyone can help me....
 

No you cannot use the digital gates at these frequencies. You need CML for the first few divide-by-2 stages and then few TSPC stages before the static CMOS dividers can be used.
 

Hello

Ayyanar M said:
Hi,

I am designing the PLL for 5GHz-6GHz applications and the reference frequency as 20MHz. So i need the divider for the range from 250-300. Is it possible to design in digital? If yes, anyone can help me....
Click to expand...

if you find out somewhat to divide by 2 , after you can use
a dedicated circuit as this one : MB506 ULTRA HIGH FREQUENCY PRESCALER
can divide by 128 or 256.
but it's maximum is 2,4GHz..

maybe others can do it..
 

thanks for urs reply...
 

Doesn't it depend on the process? In 45nm a transmission gate based FF should be fast enough?
 

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