High speed amplifier - choice of topology

[woki]

what do you meant by speed of amplifier

Hello,

Fisrt of all, I will present myself: I come from technology process and I am a beginner with analog design (I am on training now).

I need to design a unity gain amplifier working at 40 Mhz (0.35 um technology with 3.3V). The main limitation is the slew rate and settlingtime (around 40 ns today), which I need to decrease near 10/15 ns, for a global power lower than 10 mW.
Moreover, I have a very heavy load to drive (near 35 pF ...)

First, I had to choose the topology of my amplifier. I oriented my choice to telescopic (for speed and minimum power) gain boosted cascode. I do not know at his time if I will need an output stage (speed ...), if I finally need, I think use a class AB source follower.

So my first question is: Is this topology choice the best for my application ? (I heard about class AB input and output stages ...)
Or do you have a better topology proposition ?

thanks in advance.

 

[woki]

Re: High speed amplifier

Nobody have an idea ?
Little update: I am unable to drive 35 pF with a single telescopic cascode stage.
So I am currently designing a class AB output stage.
I am not sure that gain boosting will help improving the speed (slew rate, settling time) of my amplifier, what do you think ?

Thanks in advance.

Fred

 

[wael_wael]

Re: High speed amplifier

hi, i support for power supply 3.3v, telescopic amplifier only the output swing will be low. so here is comparison of amplifiers
regards

 

[woki]

Re: High speed amplifier and analog multiuplexing

Thanks for your answer.
Indeed, I saw it on Razavi's book, that's what motivated my choice.
At this time, I have another problem with this kind of amplifier: I use it for a pixel sensor application, and I need to multiplex many columns on one amplifier.
So, do anyone know a great way to realize an anlog multiplexer, with a small output capacitance ?
Thanks in advance.

Fred

 

[northeast1]

Re: High speed amplifier

Hello,

Fisrt of all, I will present myself: I come from technology process and I am a beginner with analog design (I am on training now).

I need to design a unity gain amplifier working at 40 Mhz (0.35 um technology with 3.3V). The main limitation is the slew rate and settlingtime (around 40 ns today), which I need to decrease near 10/15 ns, for a global power lower than 10 mW.
Moreover, I have a very heavy load to drive (near 35 pF ...)

First, I had to choose the topology of my amplifier. I oriented my choice to telescopic (for speed and minimum power) gain boosted cascode. I do not know at his time if I will need an output stage (speed ...), if I finally need, I think use a class AB source follower.

So my first question is: Is this topology choice the best for my application ? (I heard about class AB input and output stages ...)
Or do you have a better topology proposition ?

thanks in advance.

you should increase the current of one stage which have large cap load.

 

[woki]

Re: High speed amplifier

Thanks for your help. One of my other concerns is to maintain a power consumption lower than 10 mW.
A little update on my progression: my amplifier can drive 60 pF load with 2.8 mA current consumption near 10/12 Mhz. I still have some stability issues to study.
I hope I will be able to reach 20 Mhz increasing the current near 3mA ...
If not, I will use slew rate enhancement circuit ...

 

[rosaeidi]

High speed amplifier

Hi

Play with you transistor sizes in input stage.

 

[quaternion]

Re: High speed amplifier

Very Interesting.
I am designing a LDO, & facing somehow similar problem in the error amplifier; the load is the pass-element whose gate node has an equivalent capacitance in the range of 60pF(may be more) & I need it to be fast in order not to get large spikes & dips & to have a gain not less than 40dB(for 1stage amplifier),the difference is that I can't use more stages or I will need abnormal frequency compensation techniques (not to affect the speed), I can't stack many transistors above each others(not to use telescopic cascode) as the supply is 1.2V,& I can't dissipate large quiescent current (as I have maximum current to be driven out of the LDO is 5mA ).

So,please if you have used SRE or involoved in the frequency compensation, inform us with your progress.

 

[chanakya77]

Re: High speed amplifier

Hello ,

The available best solution for designing High Slew Rate /Ultra low power bias current Amp is using Class-AB output stage .The available Class-AB output Topologies are Floating Current Source biased Output Stage & Source Follower type Output stage .each have its own adavantages....Floating Current source biased Output Stage type Amp is like Two Stage Amp . In this if the load is not resistive ,you will get more gain Without using Any gain boosting techniques.In the case of source follower type output stage ,to get reasonable gain first stage of this configuration most probable gain boosted stage since output stage is unity gain/high slew rate buffer.

if the the design has to be optimized W.r.t power ,most probable it has to be seen differently W.r.t Slew rate and settling time .Even there is little correlation beween these two , These are reasonably independent .It is becasue Slew rate is large signal condition and settling time is small signal condition .

for high speed ,high slew rate amps optimum solution W.r.t power can be Class-AB output stage if Amp has to drive huge load cap .here you can use current buffer compensation for compensating Amp Without loosing Amp Speed significantly .Here assumption is Amp is two stage[First is gain stage & second is class-AB] &Amp has to drive huge load cap and compensation cap is placed between first stage output and class-AB output.

if the slew rate is limited by first stage output node ( Mostly occures in LDO regulators ) ..then you can go to adaptive biasing .in this case First stage of Amp increases its biasing current regeneratively if it recogizes Amp is in slweing condition.

Summarising ,Amps can be designed for High Speed ,High Slew Rate and low power by intelligently slecting available output stages & Compensation techniques.

Thanks,

 

[quaternion]

Re: High speed amplifier

...here you can use current buffer compensation for compensating Amp Without loosing Amp Speed significantly .Here assumption is Amp is two stage[First is gain stage & second is class-AB] &Amp has to drive huge load cap and compensation cap is placed between first stage output and class-AB output.

Could anyone recommend any paper or notes on current buffer compensation

if the slew rate is limited by first stage output node ( Mostly occures in LDO regulators ) ..then you can go to adaptive biasing .in this case First stage of Amp increases its biasing current regeneratively if it recognizes Amp is in slewing condition.

I didn't get what do you mean; Do you mean the 1st stage limits the slew rate by seeing large compensation cap or it draws very little current or what? I mean to limit the slew rate of the 1st stage there should be small current and large capacitive load ,but if you said first stage so you mean the EA is multistage so how will the 1st stage sees large capa. load.

what is the best adaptive biasing technique ?

 

[chanakya77]

Re: High speed amplifier

...here you can use current buffer compensation for compensating Amp Without loosing Amp Speed significantly .Here assumption is Amp is two stage[First is gain stage & second is class-AB] &Amp has to drive huge load cap and compensation cap is placed between first stage output and class-AB output.


Could anyone recommend any paper or notes on current buffer compensation

This is baisc paper on Current buffer compensation . it is improved varient of miller compensation.



if the slew rate is limited by first stage output node ( Mostly occures in LDO regulators ) ..then you can go to adaptive biasing .in this case First stage of Amp increases its biasing current regeneratively if it recognizes Amp is in slewing condition.


I didn't get what do you mean; Do you mean the 1st stage limits the slew rate by seeing large compensation cap or it draws very little current or what? I mean to limit the slew rate of the 1st stage there should be small current and large capacitive load ,but if you said first stage so you mean the EA is multistage so how will the 1st stage sees large capa. load.

Yes ..here First stage would be operating with reasonably less current ..and compensation cap loading loading first stage output . Since In LDOs ,output stage will have reasonably huge gm [I.e ,larger size] ,most of the cases ,this Amp slew rate will be limited by first stage bias current & Time constant at first stage output.

what is the best adaptive biasing technique ?

Please go thorugh this paper ...

"Adaptive biasing CMOS amplifiers" , Degrauwe, M.G.; Rijmenants, J.; Vittoz, E.A.; De Man, H.J. Solid-State Circuits, IEEE Journal of Volume 17, Issue 3, Jun 1982 Page(s): 522 - 528

 

[woki]

Re: High speed amplifier

Thank you for your help.
I tried many amplifier architectures.

The first one I used was the folded cascode with Class AB floating current source as an output stage. The major problem with that structure was it was too much power consuming. Indeed, I had to use near 3.5 mA for the folded cascode input stage and 3 mA for the Class AB output stage. I could not reach the speed and phase margin requirements with lower power consumption.

So I tried to use Telescopic cascode with the Class AB output stage (so that, I reduced the input stage power consumption by a factor 3).
But the output stage was still very power consuming (I need near 12 mA during slewing to drive my load ...).

Finally, I decided to use a single stage amplifier (telescopic for power) with SRE.
I could reach more than 20 Mhz frequency with a 65 pF cap load and a 100KOhm resistance.
I still have some troubles: the gain is reduced to 45 dB due to my resistive load and I can see an overshoot which depend of the input step amplitude (probably due to shut off of some transistors in the SRE circuit).

I think I will continue with the last structure and I will introduce gain boosting to increase the gain. And I will examine the overshoot problem (an idea).
The SRE circuit is based on Nagaraj paper (IEEE 1990: CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique).

I will post some pictures in the coming days.

Fred