high frequency clock input to an IC

[Ans5671]

Hi all,
I have read in the papers where a high-frequency (>1GHz) clock is given to an IC. Is this possible? How to overcome the effect on the clock due to Bondwires? Is the input clock given is a square wave or sine wave.

 

[danadakk]

You might look at this site and tools -

ADIsimCLK | Design Center | Analog Devices

Learn more about ADIsimCLK--a clock design tool used for predicting phase noise and jitter for Analog Devices' ultralow jitter clock distribution and clock generation products.

www.analog.com

Regards, Dana.

 

[dick_freebird]

1GHz can be pushed in as a "soft square" or sine wave
and squared up using capacitor-blocked inverter(s).
Often there is an on-chip PLL to clean up jitter and this
can also let an on chip HF clock be generated from
a lower frequency reference clock.

 

[Ans5671]

I was looking for the former method - sending in the sine signal and squaring it up with an inverter. Could you explain what do you mean by capacitor-blocked inverter(s).
The supply and ground is getting disturbed to Vpp of 0.4V. How to keep it calm (not get disturbed by the clock excursoins) inside the chip.

 

[dick_freebird]

Look for papers on "CMOS RF prescaler" and you
will see this scheme commonly used, in both
"standalone" prescaler / divider chips and as
the front end of integrated prescalers in PLLs.

Cblock goes outside, a select component.

Front end inverter is large, and either self-
biased (D=G) or replica biased (a small equal
ratio inverter held D=G, an isolation resistor
and that resistor goes to the front inverter
gates as does Cblock from outside). A low taper
(even sub-unity, in spots) factor helps with
squaring the edges.

Subsequent stages are probably DC-coupled.
You add enough stages to cover maximum
frequency, minimum input amplitude and/or
risetime and PVT variation and get an acceptably
square clock out the back.