Did you analyze first why its failing by that much large negative slack? what kind of path is it ? I2C or C2C or I2O path etc? You need to then look at the path and see if some constraints are missing ...Dont expect the tool to solve everything especially if its failing by more 30-40% of the clock period... This applies to all synthesis tools irrespective of vendor..also check how many paths are failing and whats the histogram looks like ? Is it only few paths or may be a 100 paths etc and if it is handful , then do all they have common start/end point or is it from register bank or macro paths or paths from one block to another ...check if there are any full/half adders, large multiplexers that can decomposed or huge fanout or any blocks/sub designs where preserve attr is set etc...For STA, analysis is key ..once you analyze and describe the problem more detailed, you will get more precise answers, else answers will be very generic and you will still be clueless...Good luck.