Hi, I want to design a 1024*32kbytes SRAM array with Hspice

[lilirizi]

32k bytes =

Hi everybody,

I want to design a 1024*32 kbytes SRAM array with Hspice. I have some problems:

1-How can I model long bit line wires?
2-How can I define this big circuit in Hspice 2007?
3- Do you know a paper that model the lines in SRAM?

Bests, lili

 

[rajalakshmirenold]

Re: Hi, I want to design a 1024*32kbytes SRAM array with Hsp

where to get the structure for 1024*32k sram and dram .
how to write the hspice coding?

 

[vivekniwane]

Re: Hi, I want to design a 1024*32kbytes SRAM array with Hsp

Hi there,
Best option for u will be to have overlook at

https://cmosedu.com/cmos1/hspice/hspice.htm

If u r new to hspice u'll find very helping stuff here.

Regards.

 

[dick_freebird]

Re: Hi, I want to design a 1024*32kbytes SRAM array with Hsp

I seriously doubt you want to model the entire array
with an analog circuit simulator and transistor primitives.

More likely you would want to figure out your worst case
timing events, model the paths that change in detail and
paths that don't, as simpler "dummies" - contributing (say)
line loading, where it counts, but not getting all busy when
you won't ever care what they get up to. Maybe you add
other things like leakage conductances or whatever. But
simulating more than you will review later, only wastes
a whole bunch of waiting - if the simulation manages to
finish at all.

Make subcircuit hierarchy and you can substitute these
dummies pretty simply (by just changing names).