Hi every body, I am ready to help you !!!

Status
Not open for further replies.

ok_box

Newbie level 6
Joined
Dec 29, 2004
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
59
I'm a CAD man,
please let me know, if you have any problem
 

Hi man !
I have a question about back and and anlog design tool. Have you an experience with ?
 

Dear Friend,
I have some experiences in some CAD tools

Xilinx ISE, ModelSim, ActiveHDL, Cadence IC Package, Synopsys Design Compiler and HSPICE
 

Design Compiler ! Nice.
I need your help regarding tcl scripting for design compiler. Are you familiar with ?
 

Not good, But I am familiar with Verilog HDL code
 

Verilog VHDL, no problem. I'm interrested only in the tcl scripting in particular the design constraints.
How to set them ?
How to choose clock uncertainty, frequency and Hold set up times for a DFF ?
Thanks in advance.
 

It is very kind of you, I remember you name, see if I have any qiestions~~
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…