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Hi every body, I am ready to help you !!!

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I'm a CAD man,
please let me know, if you have any problem
 

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Hi man !
I have a question about back and and anlog design tool. Have you an experience with ?
 

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Dear Friend,
I have some experiences in some CAD tools

Xilinx ISE, ModelSim, ActiveHDL, Cadence IC Package, Synopsys Design Compiler and HSPICE
 

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Design Compiler ! Nice.
I need your help regarding tcl scripting for design compiler. Are you familiar with ?
 

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Not good, But I am familiar with Verilog HDL code
 

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Verilog VHDL, no problem. I'm interrested only in the tcl scripting in particular the design constraints.
How to set them ?
How to choose clock uncertainty, frequency and Hold set up times for a DFF ?
Thanks in advance.
 

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It is very kind of you, I remember you name, see if I have any qiestions~~
 

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