Hi every body, I am ready to help you !!!

[ok_box]

I'm a CAD man,
please let me know, if you have any problem

 

[master_picengineer]

Hi man !
I have a question about back and and anlog design tool. Have you an experience with ?

 

[ok_box]

Dear Friend,
I have some experiences in some CAD tools

Xilinx ISE, ModelSim, ActiveHDL, Cadence IC Package, Synopsys Design Compiler and HSPICE

 

[master_picengineer]

Design Compiler ! Nice.
I need your help regarding tcl scripting for design compiler. Are you familiar with ?

 

[ok_box]

Not good, But I am familiar with Verilog HDL code

 

[master_picengineer]

Verilog VHDL, no problem. I'm interrested only in the tcl scripting in particular the design constraints.
How to set them ?
How to choose clock uncertainty, frequency and Hold set up times for a DFF ?
Thanks in advance.

 

[well-read]

It is very kind of you, I remember you name, see if I have any qiestions~~