[Help] XC9572XL CPLD Basic Configuration

[jjeevan007]

hi to all,

i am very new to CPLD i want to design the XC9572XL board, i don't where to start,

please can any one give me basic set up circuit of the XC9572XL,

i have gone through the datasheet but i am not able to get anything......

i have one more doubt the thus it requires any crystal oscillator or not..... just like in microcontroller...

or it has in built oscillator.....

if external oscillator is required than to which pin we have to supply.........

please help

 

[jjeevan007]

please help by going through the datasheet i am not able get configuration part....... i.e, how to supply the clock to XC9572XL.......

 

[alexan_e]

Maybe these can help

https://bitcycle.org/electronics/1st_CPLD_project/

 

[jjeevan007]

sir,

what about the clock circuit or oscillator circuit and reset circuit.............

 

[alexan_e]

For the clock you can use an external oscillator like

I'm not sure what you mean by reset circuit

 

[jjeevan007]

please can u mention the pin numbers like in 8051 pin "18 and 19" are oscillator pins

please tell me because in data sheet they didnt mention it so

 

[alexan_e]

You should download the datasheet , there is a pin list there.
There is not a specific pin for clock, in general you could use any pin but there are a few pins that are optimized for this job, the GCK pins.
They are optimized to distribute a clock signal to all macrocells with minimum skew and extra resources. If you plan to use a clock with the CPLD, connect it to one of these pins if possible.

A CPLD is not like an mcu so you should use a clock oscillator like the one in the image I have includes.

 

[jjeevan007]

how to check the operating frequency of the CPLD XC9572XL......

 

[alexan_e]

It depends on the implementation, you will get a clock report after fitting in the chip the circuit you designed , ISE will report the max frequency

 

[jjeevan007]

sir, please could u explain it......

 

[alexan_e]

The max clock frequency that you will be able to use will be different for different implementations inside the cpld.
Depending on the complexity, pins and fitting options used etc you will get a report of the max frequency you can use.

 

[jjeevan007]

just like in



please correct me if i am wrong............

i am new to FPGA and CPLD

 

[alexan_e]

A faster grade chip has a higher max frequency as a datasheet specification and will also give a higher max clock compared to a lower speed grade chip for the same implementation.

The max clock you can use in your implementation is not equal to the datasheet specification but depends on the circuit you have created inside the chip and is related to the time it takes for the clock edge to reach all the internal microcells/luts that use that clock.

 

[jjeevan007]

which means the GCK pin XC9572XL determines the operating frequency of the microcells and

"The max clock you can use in your implementation is not equal to the datasheet specification but depends on the circuit you have created inside the chip and is related to the time it takes for the clock edge to reach all the internal microcells/luts that use that clock."

is it circuit designed on board or on chip........

if it is on chip then how to know it.......

if it circuit designed on board then to which pins of XC9572XL we are applying............

 

[alexan_e]

I was referring to the internal CPLD/FPGA circuit, the one you implement using an HDL language like VHDL or Verilog, the max clock will be reported to you after the fitting process done in ISE which is the transformation of your actual code to hardware inside the chip.

This will all become clear once you make your first project with a cpld device.

 

[jjeevan007]

thank you that was really help full