[SOLVED] help with writing a testbench

[Fractional-N]

Hi,
here is my testbench:

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Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
library std;
use std.textio.all;
 
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS 
END test_tb;
 
ARCHITECTURE behavior OF test_tb IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT c4KMemory  --'c4KMemory' is the name of the module needed to be tested.
    --just copy and paste the input and output ports of your module as such. 
    PORT (
        pRESET    : in std_logic;
 
        pCLKA     : in std_logic;
        pENABLEA  : in std_logic;
        pADDRA    : in std_logic_vector(10 downto 0);
        pDATAINA  : in std_logic_vector(7 downto 0);
 
        pCLKB     : in std_logic;
        pENABLEB  : in std_logic;
        pADDRB    : in std_logic_vector(8 downto 0);
        pDATAOUTB : out std_logic_vector(31 downto 0)
    );
    END COMPONENT;
    --declare inputs and initialize them
    signal sCLK     : std_logic := '0';
    signal sRESET   : std_logic := '0';
    signal sENABLEA : std_logic := '1';
    signal sENABLEB : std_logic := '0';
    signal sADDRA       : std_logic_vector(10 downto 0) := (others => '0');
    signal sADDRB       : std_logic_vector(8 downto 0) := (others => '0');
    signal sDATAINA : std_logic_vector(7 downto 0) := X"00";
    --declare outputs and initialize them
    signal sDATAOUTB    : std_logic_vector(31 downto 0) := X"00000000";
    -- Clock period definitions
    constant clk_period : time := 1 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: c4KMemory PORT MAP (
        pRESET    => sRESET,
 
        pCLKA     => sCLK,
        pENABLEA  => sENABLEA,
        pADDRA    => sADDRA,    
        pDATAINA  => sDATAINA,  
 
        pCLKB     => sCLK,
        pENABLEB  => sENABLEB,  
        pADDRB    => sADDRB,
        pDATAOUTB => sDATAOUTB
    );
 
    -- Clock process definitions( clock with 50% duty cycle is generated here.
    clk_process : process
    begin
        sCLK <= '0';
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        sCLK <= '1';
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
    end process;
    reset_process : process
    begin
        sRESET <= '1';
        wait for 7 ns;
        sRESET <= '0';
        wait for 14 ns;
        sRESET <= '1';
    end process;
    -- Stimulus process
    stim_proc : process(sRESET,sCLK)
        file vector_file : text is "vectors";
        variable L : line;
        variable vData : integer;
        variable good_data : boolean;
    begin
            if (sRESET = '1') then
                sADDRA <= (others => '0');
                vData := 0;
                L := X"00";
              elsif (sCLK' event and sCLK = '1') then
                readline(vector_file,L);                        
                read(L,vData,GOOD => good_data);                
                sADDRA <= sADDRA + 1;
            end if;
    end process;
 
END;

---

and this is the UUT:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity c4KMemory is
    Port ( pRESET    : in std_logic;
 
           pCLKA     : in std_logic;
           pENABLEA  : in std_logic;
           pADDRA    : in std_logic_vector(10 downto 0);
           pDATAINA  : in std_logic_vector(7 downto 0);
 
           pCLKB     : in std_logic;
           pENABLEB  : in std_logic;
           pADDRB    : in std_logic_vector(8 downto 0);
           pDATAOUTB : out std_logic_vector(31 downto 0));
end c4KMemory;
 
architecture Behavioral of c4KFIFOMemory is
 
begin
   RAMB16_S9_S36_instA : RAMB16_S9_S36 -- 16K-bit with 9-bit & 36-bit input/output ports. 8-bit data 1-bit parity, 32-bit data 4-bit parity
   generic map (
      INIT_A => X"000", --  Value of output RAM registers on Port A at startup
      INIT_B => X"000000000", --  Value of output RAM registers on Port B at startup
      SRVAL_A => X"000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Port A Address 0 to 511, Port B Address 0 to 127
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 512 to 1023, Port B Address 128 to 255
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 1024 to 1535, Port B Address 255 to 383
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 1536 to 2047, Port B Address 384 to 511
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Port A Address 0 to 511, Port B Address 0 to 127
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 512 to 1023, Port B Address 128 to 255
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 1024 to 1535, Port B Address 256 to 383
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 1536 to 2047, Port B Address 384 to 511
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA   => open,         -- Port A 8-bit Data Output
      DOB   => pDATAOUTB,   -- Port B 32-bit Data Output
      DOPA  => open,         -- Port A 1-bit Parity Output
      DOPB  => open,         -- Port B 4-bit Parity Output
      ADDRA => pADDRA, -- Port A 11-bit Address Input
      ADDRB => pADDRB, -- Port B 9-bit Address Input
      CLKA  => pCLKA,        -- Port A Clock
      CLKB  => pCLKB,        -- Port B Clock
      DIA   => pDATAINA,     -- Port A 8-bit Data Input
      DIB   => X"00000000",  -- Port B 32-bit Data Input
      DIPA  => "0",          -- Port A 1-bit parity Input
      DIPB  => X"0",         -- Port B 4-bit parity Input
      ENA   => pENABLEA,    -- Port A RAM Enable Input
      ENB   => pENABLEB,    -- Port B RAM Enable Input
      SSRA  => pRESET,       -- Port A Synchronous Set/Reset Input
      SSRB  => pRESET,       -- Port B Synchronous Set/Reset Input
      WEA   => '1',          -- Port A Write Enable Input
      WEB   => '0'           -- Port B Write Enable Input
   );
    
end Behavioral;

---

when I start the simulation with ISim, I get the ERROR:

Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ERROR: In process testbech.vhd:stim_proc 
 FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
INFO: Simulator is stopped.
ERROR: In process testbech.vhd:stim_proc 
 FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
The simulator has terminated in an unexpected manner.  Please review the ISim log (isim.log) for details.

please help me resolve the problem.

 

[barry]

Have you looked at the Isim.log file like it says?

 

[Fractional-N]

Have you looked at the Isim.log file like it says?

yes
the ERROR massage I've placed in my post is the content of ISim.log file. it doesn't say much.

 

[barry]

Your problem might be because you're using both numeric_std and std.logic.arith. Don't use std.logic.arith, it is highly advised against.t

 

[TrickyDicky]

Your problem might be because you're using both numeric_std and std.logic.arith. Don't use std.logic.arith, it is highly advised against.t

Although you shouldnt mix the two libraries, I highly doubt thats whats causing the crash, as there is no signal with a signed or unsigned type. And it should complain about abiguous types, not crash like that (unless ISIM is really really badly written).

Does the file "vectors" (I note no .txt extension) exist on the system?
did you realise you're reading from a file and doing nothing with its contents?
What is the simulation resolution have you set?
you have a clock period of 1ns, which can sometimes be the simulator resolution. Did you really want it to run a 1 GHz clock?

 

[Fractional-N]

Does the file "vectors" (I note no .txt extension) exist on the system?

yes it exists.

did you realise you're reading from a file and doing nothing with its contents?

yes I know, actually I deleted some part of the code because I thought those parts might cause the problem; this code is the simplest one which just reads the contents of a file; if I be able to successfully read the contents of a file, then I would put them in RAMB and after that I'll use that RAMB as a FIFO memory.

What is the simulation resolution have you set?

copied from ISim.log:

Time resolution is 1 ps

you have a clock period of 1ns, which can sometimes be the simulator resolution. Did you really want it to run a 1 GHz clock?

well the resolution is 1ps. I've changed the clock period to 100ns and again got the problem.

I think reading the content of file causes the ERROR but I don't know what the problem is! and how I can resolve it?

P.S. thanks barry, I removed the "std.logic.arith" as you said. But still the error exists.

- - - Updated - - -

UPDATE:
the problem is because of this line:

---

Code VHDL - [expand]
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if (sRESET = '1') then
                ...
                ...
                L := X"00"; -- ERROR

---

do I need to initialize the line variable "L" ?
how should I initialize it correctly?

 

[TrickyDicky]

No, you do not need to initialise it, and this is the very problem.

the line type is a pointer to a string. Unless you know what you're doing, do NOT assign anything to it. As it's a pointer, it needs an integer, but that integer is actually a memory address. So assigning anything to it is liable to cause a memory violation at the OS level (hence the crash).

Line types can only be assigned using the "new" operator, and removed by either using the DEALLOCATE procedure (you can assign it to null, but then you get a memory leak). Both of these are done inside the readline procedure, so you dont have to do them youself.

So do not assign anything to it.