Help with vhdl code for a counter

bking said:

XOR, not OR?

Click to expand...

Jetach said:

Hello guys, I am writing vhdl code for a two timers which count in gray code. Counting up on the rising edge and the other counting up on the falling edge.

When I run a test bench of the code, it counts up correctly, but it will skip clock cycles and a weird pattern.

Here is the code and test bench results.

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity cntcore is
    Port ( enable : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           out1 : out  STD_LOGIC_VECTOR (7 downto 0);
           out2 : out  STD_LOGIC_VECTOR (7 downto 0));
end cntcore;

architecture Behavioral of cntcore is

signal count1 : std_logic_vector (7 downto 0);
signal count2 : std_logic_vector (7 downto 0);

begin

process(clk, reset, enable)
begin
	if reset = '1' then
		count1 <= "00000000";
		count2 <= "00000000";
	end if;
	
	if rising_edge(clk) then
		if reset = '0' and enable = '1' then
			count1 <= count1 + 1;
			
			out1(7) <= count1(7);
			out1(6) <= count1(7) or count1(6);
			out1(5) <= count1(6) or count1(5);
			out1(4) <= count1(5) or count1(4);
			out1(3) <= count1(4) or count1(3);
			out1(2) <= count1(3) or count1(2);
			out1(1) <= count1(2) or count1(1);
			out1(0) <= count1(1) or count1(0);
			
		end if;
	end if;

	if falling_edge(clk) then
		if reset = '0' and enable = '1' then
		count2 <= count2 + 1;
		
		out2 <= (count2(7), count2(7) or count2(6), count2(6) or count2(5),
					count2(5) or count2(4), count2(4) or count2(3), count2(3) or count2(2),
					count2(2) or count2(1), count2(1) or count2(0));
		
		end if;
	end if;
	
end process;
end Behavioral;

Any help on why the counter is not following the clock cycles would be awesome.

Click to expand...