module cicdecim64 (x_in,y_out,clk);
input clk;
input [7:0] x_in;
output [7:0] y_out;
parameter hold=0, sample=1;
reg state; //sample or hold states
reg [5:0] count; //count till 63 starting from 0
reg [7:0] x; //input
wire [23:0] sx; //sign extended input
reg [23:0] i0; //Integrator output section 0
reg [18:0] i1; //output section 1 under the consideration of Haugenauer's pruning
reg [13:0] i2;
reg [11:0] i2d1, c1, c0; // Integrator+COMB 0
reg [10:0] c1d1, c2;
reg [9:0] c2d1, c3;
always @(negedge clk)
begin : FSM // finite state machine
case (state)
hold : begin
if (count<63) // setting states for downsampling
state <= hold;
else
state <=sample;
end
default :
state <= hold;
endcase
end
assign sx={{16{x[7]}},x_in};
// Integrator
always @(posedge clk)
begin: I
x <= x_in;
i0 <= i0+sx;
i1 <= i1+i0[23:7];
i2 <= i2+i1[18:5];
case (state) //downsample
sample : begin
c0 <= i2[13:1];
count <= 0; //reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end
// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;
c1 <= c0-i2d1;
c1d1 <= c1[11:1];
c2 <= c1[11:1]-c1d1;
c2d1 <= c2[10:1];
c3 <= c2[10:1]-c2d1;
end
assign y_out=c3[9:2];
endmodule
The initialization value for reg, time, and integer data types shall be the unknown value, x.
The Verilog standard specifies
If you don't implement an explicite reset signal, you have to supply initial values to make the simulation work.
always @(posedge reset)
begin
i0<=24'd0;
i1<=19'd0;
i2<=14'd0;
end
Error (10028): Can't resolve multiple constant drivers for net "i0[23]" at wb_hp_f.v(45)
initial begin
i0<=24'd0;
i1<=19'd0;
i2<=14'd0;
end
This is the case at least for x. Why don't you trace the values of all involved variables in your simulation. That's waht simulation tools are made for.you have other signals that are undefined during the first clock edge
// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input clk,reset;
input [7:0] x_in;
output [7:0] y_out;
parameter hold=0, sample=1;
reg state; //sample or hold states
reg [5:0] count; //count till 63 starting from 0
reg [7:0] x; //input
wire [23:0] sx; //sign extended input
reg [23:0] i0; //Integrator output section 0
reg [18:0] i1; //output section 1 under the consideration of Haugenauer's pruning
reg [13:0] i2;
reg [11:0] i2d1, c1, c0; // Integrator+COMB 0
reg [10:0] c1d1, c2;
reg [9:0] c2d1, c3;
always @(negedge clk)
begin : FSM // finite state machine
case (state)
hold : begin
if (count<63) // setting states for downsampling
state <= hold;
else
state <=sample;
end
default:
state <= hold;
endcase
end
assign sx={{16{x[7]}},x_in};
// Integrator
always @(posedge clk)begin
if(reset) begin
i0 <= 24'd0;
i1 <= 19'd0;
i2 <= 14'd0;
x <= 8'd0;
end
else
x <= x_in;
i0 <= i0+sx;
i1 <= i1+i0[23:7];
i2 <= i2+i1[18:5];
case (state) //downsample
sample : begin
c0 <= i2[13:1];
count <= 0; //reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end
// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;
c1 <= c0-i2d1;
c1d1 <= c1[11:1];
c2 <= c1[11:1]-c1d1;
c2d1 <= c2[10:1];
c3 <= c2[10:1]-c2d1;
end
assign y_out=c3[9:2];
endmodule
`timescale 1ns/1ps
module test;
reg clk,reset;
reg [7:0] x;
wire [7:0] y;
cicdecim64 cic (x,y,clk,reset);
initial begin
x <=8'd1;
clk<=1'b0;
reset <= 1'b0;
#4 reset=~reset;
#5 reset=~reset;
end
always
#4 clk=~clk;
endmodule
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