note that 32'd24 is a 32 bit value, so addr width will be a concatination of 32 bit values.
One possible option is
ADDR_WIDTH => replicate(24, SLAVE_PORTS * MASTER_PORTS)
where replicate is a function you can write to return a vector of needed length with replicated content. But this not going to work either - how do you define a type of ADD_WIDTH in xyz definition?
What I want to do, is to instanciate propritary IP block coded in Verilog in my VHDL code. My question is how I define the M_ADDR_WIDTH parameter in my component declaration in VHDL?
The way I understand it, M_ADDR_WIDTH is a parameter that defines the address width of multiple master ports of a block. The block is configurable in term of number of slave port and master port. In exemple, if I set the number of master port to 4, I can define the width of each master port as Master port 1 to 28bits wide, Master port 2 to 24bits wide, Master port 3 to 16bits wide and Master port 4 to 24bit wide.
I guess the way I should define it in my component declaration should be something similar to an array type like :
type master_port_array : array of integer (1 to MASTER_PORTS) of interger range 0 to (2^^32)-1.
component xyz is
generic(
....
M_ADDR_WIDTH : master_port_array.
)
port(
...
)
** I'm not even sure I need to declarate my component before instanciate it.....
As for my component instanciation, it should be something like
generic map(
....
M_ADDR_WIDTH => (28, 24, 16, 24),
)
port map(
...
)
Am I close to a solution here? I will have to try this soon.
Interfaces between Verilog and VHDL modules is a gray area that is not really a standard. You basically need to look at your tools and see what they support. They most likely support parameters of the type integer and ports of the type std_logic_vector. So the safest bet whould be to write a system Verilog wrapper that incorporates the IP core, but has interface that is suitable for Language crossing. Then you can safely instantiate the wrapper in your VHDL module.
I agree with Ilia Kalistru that a wrapper is probably the best portable solution because it doesn't depend on mixed language capabilities of a specific tools.
In addition I have to correct a previous statement. In Verilog, the parameter ADDR_WIDTH isn't structured, e.g. an array. It's just a one-dimensional bit vector. The compatible VHDL type would be a std_logic_vector with M_PORTS*M_REGIONS*32 bits.
@Tetik. Thank you llia and FvM for your feedback. It helped me to understand replicate operator. I will proceed with a wrapper as suggested by Ilia.
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