[SOLVED] Help with Verilog replicate operator

[Tetik]

I have trouble to understand this following replicate operation in Verilog. What will be the value of ADDR_WIDTH, READ, WRITE parameters?

module xyz #(
    parameter SLAVE_PORTS         = 2,                             
    parameter MASTER_PORTS         = 4,                             
    parameter MASTER_REGIONS       = 1,
    parameter ADDR_WIDTH    = {MASTER_PORTS{{MASTER_REGIONS{32'd24}}}},
    parameter READ  = {MASTER_PORTS{{SLAVE_PORTS{1'b1}}}},     
    parameter WRITE = {MASTER_PORTS{{SLAVE_PORTS{1'b1}}}}     
)

For Write and Read, I think the final value is 8'b1111111 but what about ADDR_WIDTH? (0x18181818 ?????)

Other question, how to convert it in VHDL?

For Write and Read, something like 2**(SLAVE_PORTS * MASTER_PORTS) - 1, but here again what about ADDR_WIDTH?

Thanks for your help.

 

[ILIA KALISTRU]

note that 32'd24 is a 32 bit value, so addr width will be a concatination of 32 bit values.

One possible option is
ADDR_WIDTH => replicate(24, SLAVE_PORTS * MASTER_PORTS)
where replicate is a function you can write to return a vector of needed length with replicated content. But this not going to work either - how do you define a type of ADD_WIDTH in xyz definition?

 

[ILIA KALISTRU]

I also suspect that we have an XY problem here.
What do you want to achieve at the end?

 

[Tetik]

What I want to do, is to instanciate propritary IP block coded in Verilog in my VHDL code. My question is how I define the M_ADDR_WIDTH parameter in my component declaration in VHDL?

The way I understand it, M_ADDR_WIDTH is a parameter that defines the address width of multiple master ports of a block. The block is configurable in term of number of slave port and master port. In exemple, if I set the number of master port to 4, I can define the width of each master port as Master port 1 to 28bits wide, Master port 2 to 24bits wide, Master port 3 to 16bits wide and Master port 4 to 24bit wide.

I guess the way I should define it in my component declaration should be something similar to an array type like :

type master_port_array : array of integer (1 to MASTER_PORTS) of interger range 0 to (2^^32)-1.

component xyz is
generic(
....
M_ADDR_WIDTH : master_port_array.
)
port(
...
)
** I'm not even sure I need to declarate my component before instanciate it.....


As for my component instanciation, it should be something like
generic map(
....
M_ADDR_WIDTH => (28, 24, 16, 24),
)
port map(
...
)

Am I close to a solution here? I will have to try this soon.

Thanks.

 

[FvM]

You didn't yet show the definition of formal parameter ADDR_WIDTH in Verilog.

 

[Tetik]

You didn't yet show the definition of formal parameter ADDR_WIDTH in Verilog.

I'm a bit confused here. The ADDR_WIDTH is defined as :

---

Code Verilog - [expand]
1
parameter ADDR_WIDTH : {M_PORTS{{M_REGIONS{32'd24}}}},

---

My understanding is it's an array of array of 32bit integer with default values of 24 for each element.

In the testbench provided with the IP core, they assigned the values like this (M_PORTS is 8 and M_REGIONS is 1 in this case).

---

Code Verilog - [expand]
1
.ADDR_WIDTH    ({32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd24,32'd28})

---

Otherwise, I don't see what you are asking. The ip file doesn't show more than that.

 

[FvM]

Yes, it's an array definition. Because integer doesn't explicitely specify a bit width, I would rather use 32 bit unsigned.

 

[ILIA KALISTRU]

Interfaces between Verilog and VHDL modules is a gray area that is not really a standard. You basically need to look at your tools and see what they support. They most likely support parameters of the type integer and ports of the type std_logic_vector. So the safest bet whould be to write a system Verilog wrapper that incorporates the IP core, but has interface that is suitable for Language crossing. Then you can safely instantiate the wrapper in your VHDL module.

module xyz_wrapper #(
   ...
    parameter SLAVE0_ADDR_WIDTH    = 8,
    parameter SLAVE1_ADDR_WIDTH    = 16,
    parameter SLAVE2_ADDR_WIDTH    = 24,
    parameter SLAVE3_ADDR_WIDTH    = 10,
     ...  
)
(
    ...
    output logic [SLAVE0_ADDR_WIDTH-1 : 0] SLAVE0_ADDR;
    output logic [SLAVE1_ADDR_WIDTH-1 : 0] SLAVE1_ADDR;
    output logic [SLAVE2_ADDR_WIDTH-1 : 0] SLAVE2_ADDR;
    output logic [SLAVE3_ADDR_WIDTH-1 : 0] SLAVE3_ADDR;
    ...
)

You loose possibility to configure number of ports, of cause, but you still can configure widths.

More complicated solution is needed if you nead to dynamically configure number of ports from VHDL.

 

[FvM]

I agree with Ilia Kalistru that a wrapper is probably the best portable solution because it doesn't depend on mixed language capabilities of a specific tools.

In addition I have to correct a previous statement. In Verilog, the parameter ADDR_WIDTH isn't structured, e.g. an array. It's just a one-dimensional bit vector. The compatible VHDL type would be a std_logic_vector with M_PORTS*M_REGIONS*32 bits.

 

[Tetik]

Thank you llia and FvM for your feedback. It helped me to understand replicate operator. I will proceed with a wrapper as suggested by Ilia.

Thanks

 

[dpaul]

@Tetik.
Thank you llia and FvM for your feedback. It helped me to understand replicate operator. I will proceed with a wrapper as suggested by Ilia.
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