chasef4
Newbie level 2
Verilog Logic
Hi, I am pretty new to Verilog and was hoping someone could help me out.
I am having 2 problems, I am guessing both are related to poor logic.
1) In the example below I am getting warnings that "Warning (10235): Verilog HDL Always Construct warning at xxx.v(15): variable "D2" is read inside the Always Construct but isn't in the Always Construct's Event Control." I also get this error for D1 and ready, but not D3 which seems odd.
2) When I do a simulation, I set it to input an 8-bit binary number every 10ns. The problem is that D3 & D2 have the same value as x_in, and out[0] & out[1] have a value even in the period from 0-10ns, then change from 10-20ns. I would expect these values to be XXXXXXXX at first, since they should not be getting values yet.
module example(x_in, out)
input [7:0] x_in;
output [11:0] out[0:1];
reg signed [11:0] out[0:1];
reg [7:0] D1, D2, D3;
reg ready = 1'b1;
always @(x_in) begin
D3 = D2; D2 = D1; D1 = x_in;
if (ready)
ready = 0;
else
ready = 1;
z[0] <= (D3[0]+1'd1)**5;
z[1] <= (D2[0]+1'd1)**5;
end
endmodule
Thanks so much!
Hi, I am pretty new to Verilog and was hoping someone could help me out.
I am having 2 problems, I am guessing both are related to poor logic.
1) In the example below I am getting warnings that "Warning (10235): Verilog HDL Always Construct warning at xxx.v(15): variable "D2" is read inside the Always Construct but isn't in the Always Construct's Event Control." I also get this error for D1 and ready, but not D3 which seems odd.
2) When I do a simulation, I set it to input an 8-bit binary number every 10ns. The problem is that D3 & D2 have the same value as x_in, and out[0] & out[1] have a value even in the period from 0-10ns, then change from 10-20ns. I would expect these values to be XXXXXXXX at first, since they should not be getting values yet.
module example(x_in, out)
input [7:0] x_in;
output [11:0] out[0:1];
reg signed [11:0] out[0:1];
reg [7:0] D1, D2, D3;
reg ready = 1'b1;
always @(x_in) begin
D3 = D2; D2 = D1; D1 = x_in;
if (ready)
ready = 0;
else
ready = 1;
z[0] <= (D3[0]+1'd1)**5;
z[1] <= (D2[0]+1'd1)**5;
end
endmodule
Thanks so much!