Hi,
I will try to answer your question, If not corect feel free to coment.
The flip flop is made of feed back loop formed by invertors, In setup window the output of the flop evaluates to the desired value. The flop will stabilizes when it enters into feed back loop, the feed backing invertor need to drive the input invertor. But the output drive strength of feed back invertor is not sufficient, hence the input vlotage must be stable for hold time period until the feed backing is done to sufficient strength. If it voilates then rise time increase which evatually voilates subsequant operations. This hold time voilation can be fixed even after layout by delaying some inputs.
Thanks to all