As you see this shift register is consists of 4 dynamic d latches or two d dynamic flip-flops.
With non-overlapping clocks shift register works ok.
But when I use overlapping clocks at the output of the second inverter I get smaller voltage then
Vdd (Vdd=5v,and I get 2.5v),that's what I don't understand.
I know that with overlapping clocks all TG are on at the same time,
but I don't know how to prove how that effects that this circuit can't work with overlapping clocks?